An amplifier circuit (200) for compensating an output signal provided at an output (212) of a circuit (210) is disclosed. The amplifier circuit (200) comprises an output transmission line (230) connected between the output (212) of the circuit (210) and an output port (240) and an amplifier (220). The amplifier (220) comprises multiple sub-amplifiers (221, 222, 223, 224), inputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled to an input transmission line (250) for receiving an error signal; and outputs of the multiple sub-amplifiers (221, 222, 223, 224) are coupled at respective places along the output transmission line (230) to inject a compensation signal to the output port (240). The error signal is derived from a reference input signal and the output signal of the circuit (210), and is amplified in the amplifier (220) into the compensation signal.

An inverted three-stage Doherty amplifier is disclosed. The amplifier provides an input power divider, a carrier amplifier, two peak amplifiers, and an output combiner. The output combiner includes five quarter-wavelength (/4) lines, three of which correspond to the three amplifiers, one of which combines an output of the carrier amplifier with an output of the first peak amplifier, and the last of which combines the combined output of the carrier amplifier and the first peak amplifier with an output of the second peak amplifier. The five /4 lines have respective impedances to optionally adjust the output impedance of the respective amplifiers.

An RF power amplifier includes a quadrature coupler, an in-phase amplifier, a quadrature amplifier, and a feed-forward signal path. The quadrature coupler includes an in-phase input node, a quadrature input node, an isolated node, and an RF signal output node. The in-phase amplifier includes an in-phase amplifier output node coupled to the in-phase input node. The quadrature amplifier includes a quadrature amplifier output node coupled to the quadrature input node. The feed-forward signal path is configured to couple and condition a signal from one of the in-phase amplifier and the quadrature amplifier in order to provide a feed-forward output signal that when provided at the feed-forward output node cancels one or more harmonic signals.

Supporting suppression of distortion caused by a power amplifier, PA, included in a transmitter system configured to perform digital predistortion, DPD, and feedforward, FF, linearization on multiple digital input signals relating to different frequency bands, respectively. The PA is used for power amplification in preparation for transmission by a wireless communication network and is operative with an instantaneous bandwidth, IBW. Information is obtained identifying one or more intermodulation, IM, components outside the frequency bands but within the IBW, and caused by said PA. The identified IM components are selectively processed as part of said DPD to thereby suppress formation of at least some of the identified IM components, and/or as part of the FF linearization by adding reference signals to the FF linearization, which reference signals correspond to at least some of the identified IM components.

A power amplifier (20) for a transmitter circuit (10) is disclosed. The power amplifier (20) comprises at least one field-effect transistor (100, 100n, 100p) having a gate terminal (110, 110n, 110p) and a bulk terminal (120, 120n, 120p), wherein the at least one field-effect transistor (100, 100n, 100n) is configured to receive an input voltage at the gate terminal (110, 110p, 110n) and a dynamic bias voltage at the bulk terminal (120, 120n, 120p). Furthermore, the power amplifier (20) comprises a bias-voltage generation circuit (130). The input voltage is a linear function of an input signal. The bias-voltage generation circuit (130) is configured to generate the dynamic bias voltage as a nonlinear function of an envelope of the input signal.

Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.

A Cartesian loop circuit includes a reference signal amplifier, a forward path coupled to the reference signal amplifier, a feedback path coupled to the forward path, and a controller. The forward path includes an up-mixer to up mix a forward path signal to a radio frequency signal. The feedback path includes a down-mixer to down mix a feedback signal to a frequency of a baseband reference signal inputted to the forward path. The feedback path provides the down-mixed feedback signal to the forward path. The controller is to perform power control at a low power by controlling a gain of the reference signal amplifier and is to perform power control at a high power by controlling a gain of the down-mixer. At the high power, the controller may perform power control by further controlling the gain of the up-mixer.

A wideband, frequency agile, radio frequency digital-to-analog converter (RF-DAC) based phase modulator includes first, second, and third RF-DACs, each configured to upconvert an input I/Q digital baseband signal pair to a local oscillator (LO) frequency but with the first RF-DAC being driven by a first set of LO clocks, the second RF-DAC being driven by a second set of LO clocks that is forty-five degrees out of phase with respect to the first set of LO clocks, and the third RF-DAC being driven by a third set of LO clocks that is a further forty-five degrees out of phase with respect to the second set of LO clocks. First, second, and third upconverted analog signals produced by the first, second, and third RF-DACs are combined to reinforce the fundamental LO component while canceling 3.sup.rd-order and 5.sup.th-order LO harmonics.

Certain aspects of the present disclosure generally relate to a differential amplifier implemented using a complementary metal-oxide-semiconductor (CMOS) structure. The differential amplifier generally includes a first pair of transistors and a second pair of transistors coupled to the first pair of transistors. The gates of the first pair of transistors and gates of the second pair of transistors may be coupled to respective differential input nodes of the differential amplifier, and drains of the first pair of transistors and drains of the second pair of transistors may be coupled to respective differential output nodes of the differential amplifier. In certain aspects, the differential amplifier may include a biasing transistor having a drain coupled to a source of a transistor of the first pair of transistors and having a gate coupled to a common-mode feedback (CMFB) path of the differential amplifier.

A power amplifying apparatus includes a first bias circuit configured to generate a first bias current, a first amplification circuit, configured to receive the first bias current, amplify a signal input to the first amplification circuit through a first node, and output a first amplified signal to a second node, a second bias circuit, configured to generate a second bias current which has a magnitude different from a magnitude of the first bias current, and a second amplification circuit, connected in parallel with the first amplification, configured to receive the second bias current, amplify the signal input through the first node, and output a second amplified signal to the second node. The second amplification circuit is configured to output the second amplified signal with a third-harmonic component that has a phase offsetting a third-order intermodulation distortion (IM3) component included in the first amplified signal, based on the second bias current.