An internal voltage offset between a positive input and a negative input of a first operational amplifier is compensated. The negative input and the positive input of the first operational amplifier are coupled at the same voltage level. A comparison current generated at an output of the first operational amplifier has a sign that is representative of a sign of the internal voltage offset. The output of the first operational amplifier is biased to a threshold voltage using a current-to-voltage converter. A control voltage is generated from a sum of the threshold voltage and a voltage conversion of the comparison current. Compensation for the internal voltage offset between the positive and negative inputs of the first operational amplifier is made dependent on the control voltage.

An amplifying circuit including a first gain circuit, a second gain circuit, a Miller capacitor, a positive feedback circuit and a feedforward gain circuit. The second gain circuit is configured to receive a first gain signal from the first gain circuit and generate a second gain signal. The Miller capacitor, the positive feedback circuit and the feedforward gain circuit are electrically coupled between an input terminal and an output terminal of the second gain circuit. The positive feedback circuit is configured to feedback the signal of the output terminal of the second gain circuit to the input terminal of the second gain circuit. The feedforward gain circuit is configured to amplify the first gain signal to output a third gain signal to the output terminal of the second gain circuit.

An amplifier includes a first capacitor connected between an input node and a floating node, a second capacitor connected between the floating node and an output node, an amplifying element connected between a power supply voltage and the output node and operating in response to a voltage level of the floating node, a current bias source connected between the output node and a ground voltage, a first reset switch connected between the floating node and an intermediate node and operating in response to a reset bias, a second reset switch connected between the intermediate node and the output node and operating in response to the reset bias, and a reset bias generator circuit that outputs the reset bias in response to a reset signal. The reset bias is one of a reset voltage of the intermediate node, the power supply voltage, and the ground voltage.

According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance microstrip is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit. In an embodiment, a greater series or source feedback is provided at a later stage of a multistage amplifier circuit, whereas a smaller series or source feedback is provided at an earlier stage of the multistage amplifier circuit.

A common-mode feedback circuit for a fully differential amplifier comprises first (M.sub.B), second (M.sub.TP), and third (M.sub.TN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (M.sub.B) and the gate terminals of the first, second, and third transistors (M.sub.B, M.sub.TP, M.sub.TN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (M.sub.B) is arranged to receive a common-mode reference voltage input (V.sub.CM), the back-gate terminal of the second transistor (M.sub.TP) is arranged to receive a positive output voltage (V.sub.P) from the fully differential amplifier, and the back-gate terminal of the third transistor (M.sub.TN) is arranged to receive a negative output voltage (V.sub.N) from the fully differential amplifier.

A reconfigurable amplifier configured to decrease radio frequency (RF) signal distortion and increase dynamic range is disclosed. The reconfigurable amplifier includes an amplifier having an RF signal input, an RF signal output, and a bias signal input. A distortion detection network has a detector input coupled to the RF signal output and a detector output, wherein the distortion detector network is configured to generate a detection signal that is proportional to distortion at the RF signal output. A bias controller has a detection signal input coupled to the detector output and a bias output coupled to the bias signal input. The bias controller is configured to generate a bias signal that dynamically shifts level at the bias output to reduce the distortion at the RF signal output in response to the detection signal.

An amplifier has a first amplifying circuit configured to receive a voltage input and to output an amplified current, a second amplifying circuit configured to receive the amplified current and to output an amplified voltage, the second amplifying circuit comprising a pair of feedback resistive elements, each feedback resistive element being coupled to a gate and drain of a corresponding transistor in a pair of output transistors in the second amplifying circuit, and a feedback circuit configured to provide a negative feedback loop between an input and an output of the pair of output transistors, the feedback circuit including a first transconductance amplification circuit and a first equalizing circuit.

An amplifying circuit including a first gain circuit, a second gain circuit, a Miller capacitor, a positive feedback circuit and a feedforward gain circuit. The second gain circuit is configured to receive a first gain signal from the first gain circuit and generate a second gain signal. The Miller capacitor, the positive feedback circuit and the feedforward gain circuit are electrically coupled between an input terminal and an output terminal of the second gain circuit. The positive feedback circuit is configured to feedback the signal of the output terminal of the second gain circuit to the input terminal of the second gain circuit. The feedforward gain circuit is configured to amplify the first gain signal to output a third gain signal to the output terminal of the second gain circuit.

An amplifying apparatus includes a transistor arranged on a substrate and constituting an amplifier, an input terminal for inputting a high-frequency signal to the amplifier, an output terminal for outputting the high-frequency signal amplified by the amplifier, a first inductor formed in or on the substrate and connected between a source of the transistor and a ground, and a second inductor formed in or on the substrate and connected between a gate of the transistor and the input terminal. When the substrate is viewed in a plan view, the first inductor and the second inductor do not overlap each other. The first inductor and the second inductor are magnetically coupled to each other.

A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.