An audio signal modulation and amplification circuit includes a common-mode electric potential controller, a carrier generator, and channel circuits. The common-mode electric potential controller is configured to generate one or more first common-mode electric potentials and second common-mode electric potentials. The carrier generator is adapted to receive the first common-mode electric potential to generate a carrier signal. Each of the channel circuits includes a filter, a comparison circuit, and a driving circuit. The filter is adapted to filter an input signal and generate a filtered signal based on a corresponding one of the second common-mode electric potentials. The comparison circuit is configured to compare the potential of the carrier signal with the potential of the filtered signal to generate a pulse-width modulation signal. The driving circuit is configured to be turned on or off in response to the pulse-width modulation signal to output a load driving signal.

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

An amplifier circuit with an overshoot suppress scheme is provided. The amplifier circuit includes an input amplifier, an output amplifier and a diode device. The output amplifier is coupled to the input amplifier and outputs an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

A circuit comprising: an input terminal; a first amplifier coupled to the input terminal of the circuit to receive an input signal; a first inductor having a first terminal coupled to the input terminal and a second terminal configured to be coupled to the ground terminal, wherein the first inductor is arranged with a second inductor and configured to magnetically couple therewith, wherein said second inductor is coupled to the first amplifier and is configured to sense a current through the amplifier.

A power amplifier has an amplifier cell with an input terminal receiving an input signal and an output terminal providing an output signal. A bias network is coupled to the output terminal of the amplifier cell to provide a bias signal to the amplifier cell. A shutdown circuit is coupled to the bias network to disable the bias network in response to the input signal. The shutdown circuit has a transistor with a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal. The shutdown circuit further has a first resistor with a first terminal coupled to the input terminal, and a second resistor with a first terminal coupled to a second terminal of the first resistor at a node, and a second terminal coupled to the power supply terminal. The control terminal of the transistor is coupled to the node.

The apparatus includes a first transistor having a gate/base terminal to receive a first drive control signal used for controlling a driver stage of the transceiver and a drain/collector terminal coupled to a control terminal of a switch of the transceiver. The first transistor is switched on when the first drive control signal is at a first level that enables the driver stage to amplify a first RF signal. When the first transistor is switched on, the drain/collector terminal of the first transistor outputs to a control terminal of the switch a switch control signal at a second level that enables the switch to provide a portion of the RF signal reflected by the antenna to the load.

The present disclosure relates to current control circuitry for controlling a current through a load, the current control circuitry comprising: amplifier circuitry; reference voltage generator circuitry configured to supply a fixed reference voltage to a first input of the amplifier circuitry; an output stage comprising: a control terminal coupled to an output of the amplifier circuitry; a current input terminal configured to be coupled to the load; a current output terminal; a clock-controlled variable resistance coupled to the current output terminal of the output stage, wherein a resistance of the variable resistance is based on a digital code input to the variable resistance; and a feedback path between the current output terminal of the output stage and a second terminal of the amplifier circuitry for providing a feedback voltage to a second input of the amplifier circuitry.

An amplification circuit has a field effect transistor, an input side matching circuit, an output side matching circuit, a capacitor, and a resistor. The input side matching circuit is connected between an input port and the source terminal of the field effect transistor and outputs an input signal that changes with a bias voltage as a center value. The output side matching circuit is connected between an output port and the drain terminal of the field effect transistor. The capacitor is connected between the gate terminal of the field effect transistor and a first reference voltage source. The resistor is connected between the gate terminal of the field effect transistor and the first reference voltage source.

A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks. The sense amplifier circuit also comprises: a first-common-mode-voltage-resistor connected in series between a first-sensed-output-terminal and a common-mode-voltage-node; and a second-common-mode-voltage-resistor connected in series between a second-sensed-output-terminal and the common-mode-voltage-node.