A DC offset cancellation circuit and a DC offset cancellation method are disclosed. The DC offset cancellation circuit comprises a high-speed amplifier, a voltage comparator, a microprocessor, and a digital-to-analog converter. The high-speed amplifier comprises an input stage with a DC offset cancellation function, an amplification stage, and an output buffer stage. The voltage comparator is connected to the output buffer stage. The microprocessor is connected to the voltage comparator. The digital-to-analog converter is connected to the microprocessor. The digital-to-analog converter is connected to the input stage.

A semiconductor amplifier circuit has a driver that outputs a drive signal corresponding to an input signal and switches drive capability of the drive signal in accordance with a logic of an instruction signal, an instruction signal setting unit that sets the logic of the instruction signal in accordance with whether the input signal satisfies a predetermined condition, and an output circuit that comprises a control terminal to which the drive signal is input and an output terminal that outputs a signal obtained by amplifying the input signal.

A semiconductor amplifier circuit has a driver that outputs a drive signal corresponding to an input signal and switches drive capability of the drive signal in accordance with a logic of an instruction signal, an instruction signal setting unit that sets the logic of the instruction signal in accordance with whether the input signal satisfies a predetermined condition, and an output circuit that comprises a control terminal to which the drive signal is input and an output terminal that outputs a signal obtained by amplifying the input signal.

Thermal temperature sensors for power amplifiers are provided herein. In certain implementations, a semiconductor die includes a compound semiconductor substrate, and a power amplifier including a plurality of field-effect transistors (FETs) configured to amplify a radio frequency (RF) signal. The plurality of FETs are arranged on the compound semiconductor substrate as a transistor array. The semiconductor die further includes a semiconductor resistor configured to generate a signal indicative of a temperature of the transistor array. The semiconductor resistor is located adjacent to one end of the transistor array.

A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.

Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency (RF) amplifiers. In some embodiments, an RF amplifier circuit includes an amplification path implemented to amplify an RF signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the RF amplifier circuit includes a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.

Circuits, methods and devices are disclosed, related to fast turn-on of radio-frequency (RF) amplifiers. In some embodiments, an RF amplifier circuit includes an amplification path implemented to amplify an RF signal, where the amplification path includes a switch and an amplifier. In some embodiments, each of the switch and the amplifier are configured to be ON or OFF to thereby enable or disable the amplification path, respectively. In some embodiments, the RF amplifier circuit includes a compensation circuit coupled to the amplifier, where the compensation circuit is configured to compensate for a slow transition of the amplifier between its ON and OFF states resulting from a signal applied to the switch.

A semiconductor device is provided with: a field-effect transistor that has a source electrode and a drain electrode that are connected to a semiconductor layer, a gate electrode that is provided on the surface of the semiconductor layer between the source electrode and the drain electrode, and a field plate electrode that is provided on the surface of the semiconductor layer in the vicinity of the gate electrode via an insulating layer, wherein the field-effect transistor amplifies high frequency signals received by the gate electrode to be outputted from the drain electrode; and a voltage dividing circuit that divides a potential difference between the drain electrode and a reference potential GND, and applies a bias voltage such that respective parts of the field plate electrode have a mutually equal potential.

A semiconductor device is provided with: a field-effect transistor that has a source electrode and a drain electrode that are connected to a semiconductor layer, a gate electrode that is provided on the surface of the semiconductor layer between the source electrode and the drain electrode, and a field plate electrode that is provided on the surface of the semiconductor layer in the vicinity of the gate electrode via an insulating layer, wherein the field-effect transistor amplifies high frequency signals received by the gate electrode to be outputted from the drain electrode; and a voltage dividing circuit that divides a potential difference between the drain electrode and a reference potential GND, and applies a bias voltage such that respective parts of the field plate electrode have a mutually equal potential.

An audio reproduction apparatus is shown and includes an amplifier with a power amplification stage having transistors in a push-pull arrangement. A bias generator biases the transistors with a standing current. A processor receives a data stream comprising digital samples of an analog audio signal and analyzes the peak level of each group. It then determines the appropriate standing currents to maintain Class A operation of the power amplification stage given the peak levels of each of the groups. A digital to analog converter produces an analog input signal for the input stage of the amplifier from the data stream. A feedforward path between the processor and the bias generator allows the standing current to be adjusted prior to the arrival of the analog input signal in the power amplification stage.