An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

An active load stage converts a first input current and a second input current into a first voltage and a second voltage. A driver amplifier operates upon receiving the first voltage and the second voltage from the active load stage, and outputs a current to an output terminal. The driver amplifier has a first transistor and a second transistor connected in series between a first reference potential terminal and a second reference potential terminal. The first transistor receives the first voltage at a gate and passes a first current, and the second transistor receives the second voltage at a gate and passes a second current. A minimum selector provides feedback to the first voltage and the second voltage such that an absolute value of each of the first current and the second current becomes more than or equal to a quiescent current of the driver amplifier.

A mobile device can have a transceiver configured to generate a radio frequency signal and a power management system with envelope tracking. The device can also have a power amplifier system having a driver transistor coupled to a radio frequency signal input, a transformer balun having a main primary coil connected between the driver transistor and a voltage supply node of the power amplifier system, a secondary coil magnetically coupled to the main primary coil and an additional primary coil configured to generate a feedback signal related to a signal of the main primary coil. The power amplifier system can also have a push-pull amplifier with a first transistor having a base connected to a first end of the secondary coil and a second transistor having a base connected to a second end of the secondary coil. Accordingly, push-pull stage neutralization can deploy two transistors cross-connected to opposite ends of an output coil in a transformer balun.

Example embodiments relate to push-pull class E amplifiers. One example push-pull class E amplifier includes an input configured for receiving a signal to be amplified. The push-pull class E amplifier also includes an output configured for outputting the signal after amplification. Additionally, the push-pull class E amplifier includes a printed circuit board having a first dielectric layer and a second dielectric layer. Further, the push-pull class E amplifier includes a first amplifying unit and a second amplifying unit. Yet further, the push-pull class E amplifier includes a balun, a capacitive unit, a first line segment, a second line segment, a third line segment, and a fourth line segment. The first line segment and the second line segment are arranged on the first dielectric layer. A combined length of the third line segment and the fourth line segment corresponds to a quarter wavelength of an operational frequency of the amplifier.

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.

A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion αVin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.

A dual-drive power amplifier (PA) where the PA core includes a differential pair of transistors M1 and M2 that are driven by a coupling network having two transmission-line couplers, where a first transmission line section of a coupler is configured to transmit an input signal Vin through to drive a gate of the opposite transistor, while the second transmission line section is grounded at one end and coupled with the first transmission line section such that a coupled portion aVin of the input signal Vin drives the source terminal of a corresponding transistor. The arrangement of the coupling network allows the source terminals to be driven below ground potential. Embodiments disclosed here further provide an input matching network, a driver, an inter-stage matching network, and an output network for practical implementation of the PA core.

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.

Embodiments of active baluns are disclosed. In an embodiment, an active balun includes input terminals configured to receive a single-ended input signal and a linear redriver configured to transform the single-ended input signal into a differential output signal.

A push-pull power amplifier (PA) includes a pair of P-type transistors, a pair of N-type transistors, and a splitter, wherein source terminals of the pair of P-type transistors are coupled to a first reference voltage, source terminals of the pair of N-type transistors are coupled to a second reference voltage, and drain terminals of the pair of P-type transistors and drain terminals of the pair of N-type transistors are coupled to an output port of the push-pull PA. The splitter is arranged to receive a common-mode input pair, and provide two differential output pairs to the pair of P-type transistors and the pair of N-type transistors, wherein one of the two differential output pairs is provided to gate terminals of the pair of P-type transistors, and the other of the two differential output pairs is provided to gate terminals of the pair of N-type transistors.