Patent classifications
H03F3/3001
LOW POWER BUFFER WITH DYNAMIC GAIN CONTROL
The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
Low noise amplifier and chip
A low noise amplifier and a chip. The amplifier includes a biasing circuit unit, a first amplifying circuit unit, a first adjusting unit, a first signal input, a second signal input and a first signal output; the biasing circuit unit includes a first voltage output and a second voltage output; the first amplifying circuit unit includes a first N-type transistor, a first P-type transistor, a first output capacitor, a second output capacitor, a first impedance and a second impedance; gates of first N-type and P-type transistors are connected to first voltage output and first signal input, and second voltage output and first signal input, respectively, via adjusting unit; source of first N-type transistor is connected to source of first P-type transistor and second signal input; drains of first N-type and P-type transistors are connected respectively to impedance, and to first signal output and second signal output via output capacitor.
Low power buffer with dynamic gain control
The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
High linearity push-pull common-gate amplifier
An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.
PUSH-PULL AMPLIFIER WITH FEEDBACK CANCELLATION
The example embodiments are directed to a push-pull amplifier embedded with cross-coupled transistor feedback cancellation. In one example, the amplifier may include a first load, a second load, a circuit comprising first and second field effect transistors (FETs) that are electrically coupled to each other and that are electrically coupled to the first load and the second load, and a feedback cancellation circuit that interconnects the first and second FETs and comprises coupling capacitors configured to increase gain, circuit stability, and Power Added Efficiency (PAE) from the first and second FETs.