LNA circuitry includes an input node, and output node, a primary amplifier stage, a first ancillary amplifier stage, and an input gain selection switch. The primary amplifier stage is configured to provide a first gain response between a primary amplifier stage input node and a primary amplifier stage output node, wherein the primary amplifier stage input node is coupled to the input node and the primary amplifier stage output node is coupled to the output node. The first ancillary amplifier stage is configured to provide a second gain response between a first ancillary amplifier stage input node and a first ancillary amplifier stage output node, wherein the first ancillary amplifier stage output node is coupled to the primary amplifier stage output node. The input gain selection switch is coupled between the input node and the first ancillary amplifier stage input node.

A power amplifier circuit includes a power splitter, a first amplifier configured to output a first amplified signal from a first output terminal, and a second amplifier configured to output a second amplified signal from a second output terminal. The power amplifier circuit further includes a first termination circuit connected between the first output terminal and the second output terminal, a first transmission line, a second transmission line, a second termination circuit connected between another end of the first transmission line and another end of the second transmission line, and a power combiner.

A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

To provide a high-frequency circuit and a communication device by which a harmonic component in differential amplification can be attenuated. The high-frequency circuit includes a differential amplifier circuit. The differential amplifier circuit includes a first amplifying element, a second amplifying element, first wiring, second wiring, and a series circuit. The first amplifying element includes a first input terminal and a first output terminal. The second amplifying element includes a second input terminal and a second output terminal. The first wiring is connected to the first output terminal. The second wiring is connected to the second output terminal. The series circuit is connected between the first wiring and the second wiring. The series circuit includes a first inductor, a second inductor, and a capacitor.

A distributed active transformer includes an input transformer set and an output transformer set. Active stages are coupled between a transformer in the input transformer set and a transformer in the output transformer set. The input and output transformer sets are each configured as a slab transformer. The input slab transformer includes a single primary slab and many secondary slabs. The output slab transformer includes many primary slabs and a single secondary slab.

An ultra-high frequency power combiner according to the disclosure includes a first input line connected to a first input port, a second input line connected to a second input port, an output line connected to an output port, a first transmission line between the first input line and the output line, a second transmission line between the second input line and the output line, a first series capacitor, a resistor, and a second series capacitor connected in series between a first node between the first input line and the first transmission line and a second node between the second input line and the second transmission line, and a first parallel capacitor, an inductor, and a second parallel capacitor connected in parallel with the resistor and connected in series with one another.

A Spatial Power Combining Amplifier (SPCA) exhibiting a new concept for the amplification of coherent (e.g., microwave) radiation. A general description of the SPCA a power analysis at various SPCA stages is provided. A successfully tested S-band SPCA example was able to deliver 120 W of power with a gain of 50 dB and 50 percent efficiency.

The isolated port of a 0/90 degree coupler is terminated by a novel complex termination impedance circuit having a reactance. The absolute value of the reactance is at least two ohms. The coupler receives a signal on its input port, and outputs a first signal on its first output port and a second signal on its second output port. A first load is coupled to the first output port without an intervening matching network. A substantial impedance mismatch exists between the first output port and the first load. A second load is coupled to the second output port without an intervening matching network. A substantial impedance mismatch exists between the second output port and the second load. Despite the substantial impedance mismatches, the first and second signals have a phase difference in a range of from 88 degrees to 92 degrees while exhibiting an amplitude imbalance less than 2 dB.

Disclosed is a Doherty power amplifier. At least one power amplification tube and other power amplification tubes in the Doherty power amplifier are located in different planes.

A power converter converts a digital input signal into an RF output power signal. A digital signal processor converts the input signal into one or more copies of a multi-bit RF signal. Each copy of the multi-bit RF signal is applied to a corresponding multi-bit current generator having a set of weighted, switched current sources, each of which is controlled by a different bit of the multi-bit RF signal. The currents from the different current sources are processed and combined to generate the output power signal.