A power combiner circuit comprises a network topology for broadband RF and microwave systems that includes coupling elements, internodal matching sections, and an output matching section. The network topology serves as a combining mechanism for power from multiple power amplifiers. The network topology is designed so that characteristic impedances of transmissions lines serving as the coupling elements, internodal matching sections, and an output matching section produce a load impedance at an output port that is matched to the impedances seen by each power amplifier providing power to the power combiner circuit. Such a network topology is scalable to an unlimited number of power amplifiers, and enables a desired broadband frequency response for power amplification, while realizing a very low level of power output loss between input and output ports.

CRLH lines including left-handed shunt inductors and left-handed series capacitors are provided on gate side transmission lines of a plurality of FETs.

In one aspect, a power amplifier apparatus comprising a power amplifier (PA) and an adaptive controller is provided. The PA comprises at least one transistor and the adaptive controller is configured to control a bias voltage of the transistor based on a measured power efficiency of the PA and a measure output signal quality of the PA. In another aspect, a method of optimizing PA performance is provided. The PA comprises at least one transistor and the method includes initializing a bias voltage of the transistor, receiving measurements indicating a power efficiency and an output signal quality of the PA, evaluating the received measurements, calculating a new bias voltage for the transistor based on the evaluation, and applying the calculated new bias voltage to the transistor.

An envelope tracking (ET) circuit is provided. In examples discussed herein, the ET circuit can be configured to operate in a fifth-generation (5G) standalone (SA) mode and a 5G non-standalone (NSA) mode. In the SA mode, the ET circuit can enable a first pair of ET power amplifier circuits to amplify a 5G signal based on ET for concurrent transmission in a 5G band(s). In the NSA mode, the ET circuit can enable a second pair of ET power amplifier circuits to amplify an anchor signal and a 5G signal based on ET for concurrent transmission in an anchor band(s) and a 5G band(s), respectively. As such, the ET circuit may be provided in a 5G-enabled wireless communication device (e.g., a 5G-enabled smartphone) to help improve power amplifier linearity and efficiency in both 5G SA and NSA networks.

The present disclosure relates to an integrated wideband Radio Frequency (RF) amplifier, based on a complementary metal oxide semiconductor (CMOS) technology. In an embodiment the amplifier addresses the shortcomings of conventional wideband amplifiers and is based on a distributed amplifier (DA) topology which typically exhibit severe performance degradation when externally loaded with parasitic circuit elements. In an embodiment of the present invention a buffer amplifier at the output of a conventional DA is able to compensate the impact of parasitic elements. The disclosed circuit can be implemented by fabricating the wideband RF amplifier integrated circuit (IC) on a 130 nm CMOS technology or other comparable CMOS technologies.

Embodiments of a multiple-path amplifier (e.g., a Doherty amplifier) and a module housing the amplifier include a first amplifier (or first power transistor die) with a first output terminal, a second amplifier (or second power transistor die) with a second output terminal, and an impedance inverter line assembly electrically connected between the first and second output terminals. The impedance inverter line assembly includes a first transmission line and a surface mount component connected in series between the first and second output terminals. In various embodiments, the surface mount component is selected from a fixed-value capacitor, a fixed-value inductor, a tunable capacitor, a tunable inductor, and a tunable passive component network.

Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures, and a power amplifier and switch can be integrated onto a single complementary metal oxide semiconductor die.

A power amplifier (100, 200, 500, 800, 1100) for amplifying an input signal into an output signal is disclosed. The power amplifier (100, 200, 500, 800, 1100) comprises an input port (110) for receiving the input signal and an output port (130) coupled to an output transmission line (140) for providing the output signal. The power amplifier (100, 200, 500, 800, 1100) further comprises multiple sets of sub-amplifiers (150, 160, 170, 180) distributed along the output transmission line, and inputs of the subamplifiers are coupled to the input port, outputs of the sub-amplifiers are coupled to the output transmission line. At least two different supply voltages are provided for the sub-amplifiers in the multiple sets of sub-amplifiers (150, 160, 170, 180).

Aspects of a distributed Darlington pair amplifier are described. In one example, a distributed amplifier device includes a number of distributed amplifier cells. The distributed amplifier cells can each include an input coupled to an input line and an output coupled to an output line. The amplifier device also includes a radio frequency input coupled to the input line and a radio frequency output coupled to the output line. One or more of the distributed amplifier cells can include a Darlington transistor pair rather than a common source transistor. The Darlington transistor pair can have a smaller gate-source capacitance than the common source transistor. This results in the ability to omit a series capacitor used with the common source transistor, improving the noise figure and gain over a range of operating frequencies for the distributed Darlington pair amplifier.

A unit amplifier has first and second transistors, which are cascode-connected, and a first variable resistance circuit. A base terminal or a gate terminal of the first transistor is connected to a cell input terminal, a collector terminal or a drain terminal of the second transistor is connected to a cell output terminal, an emitter terminal or a source terminal of the second transistor is connected to a collector terminal or a drain terminal of the first transistor, and one end of the first variable resistance circuit is connected to a connecting point of the first and second transistors.