A method for modelling a power amplifier, including memory effect modelling, for general input waveforms and power levels involves generating an extraction waveform having a plurality of tones each having a different frequency, a difference between the frequencies of two adjacent tones of the plurality of tones not being an integer multiple of a difference in frequency between any two other adjacent tones of the plurality of tones. The method further involves providing the extraction waveform to the power amplifier, receiving output from the power amplifier generated in response to the extraction waveform, and generating a model of the power amplifier based on the output.

Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p.sub.1, p.sub.2, . . . , p.sub.k} and a second set of values {s.sub.1, s.sub.2, . . . , s.sub.k} that represent a LUT value of s.sub.1.Math.2.sup.p.sup.1+s.sub.2.Math.2.sup.p.sup.2+ . . . +s.sub.k.Math.2.sup.p.sup.k where each value s.sub.i∈{+1,−1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p.sub.1, p.sub.2, . . . , p.sub.k} and {s.sub.1, s.sub.2, . . . , s.sub.k} to provide an output sample.

The disclosed technology relates generally to semiconductor devices, and more particularly to power semiconductor devices in which effects of charge trapping are compensated. A radio frequency (RF) power transmitter system comprises a RF power semiconductor device that outputs a time-varying gain characteristic from a RF signal input waveform originating from a digital input, wherein the time-varying gain characteristic includes a gain error associated with charge-trapping events having a memory effect on the RF power semiconductor device lasting longer than 1 microsecond. The RF power transmitter system further comprises circuitry configured to apply an analog gate bias waveform to the RF power semiconductor device based on the time-varying gain characteristic to reduce the gain error.

Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p.sub.1, p.sub.2, . . . , p.sub.k} and a second set of values {s.sub.1, s.sub.2, . . . , s.sub.k} that represent a LUT value of s.sub.1.Math.2.sup.p.sup.1+s.sub.2.Math.2.sup.p.sup.2+ . . . +s.sub.k.Math.2.sup.p.sup.k where each value s.sub.i∈{+1,−1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p.sub.1, p.sub.2, . . . , p.sub.k} and {s.sub.1, s.sub.2, . . . , s.sub.k} to provide an output sample.

A distortion compensation device includes: a first distortion compensation circuit having a first distortion compensation characteristic for compensating for a first distortion occurring in an output of an amplifier, the first distortion compensation circuit being configured to compensate for the first distortion; a second distortion compensation circuit having a second distortion compensation characteristic for compensating for a second distortion occurring in the output of the amplifier, the second distortion compensation circuit being configured to compensate for the second distortion; and an update unit configured to update the second distortion compensation characteristic. The first distortion includes a non-linear distortion and a memory effect distortion, the second distortion is a distortion whose temporal change is quicker than the first distortion, and the update unit updates the second distortion compensation characteristic at a higher frequency than an update frequency of the first distortion compensation characteristic.

Systems comprising a low power Digital Predistortion (DPD) system and methods of operation thereof are disclosed herein. In some embodiments, a system comprises a DPD system for digitally predistorting an input signal to provide an output signal. The DPD system comprises a DPD actuator comprising one or more configurable multiplication functions, each configurable to operate in different power modes. The different power modes comprise a first power mode in which the configurable multiplication function multiplies a first value related to an input sample of the input signal and a second value related to a respective DPD value to provide an output value and a second power mode in which the configurable multiplication function outputs, as the output value, are an approximation of a multiplication of the first value and the second value.