An amplifier operates to provide a high output impedance at an output through a push stage having a first transistor of a first transistor type and a pull stage having a second transistor of a second transistor type that is different from the first transistor type. The first transistor and the second transistor are coupled in a common-gate configuration. The first transistor and the second transistor are shorted together via a capacitor coupled to an input and share a common current path as a push-pull current-reusing common-gate low noise amplifier with a broadband input matching.

A capacitor weighted segmentation buffer includes a push-pull buffer circuit and a plurality of capacitors. The capacitors include a first capacitor having a first terminal coupled to a control terminal of the first transistor and a second terminal arranged to receive a first input signal; a second capacitor having a first terminal coupled to a control terminal of the second transistor and a second terminal arranged to receive the first input signal; a third capacitor having a first terminal coupled to the control terminal of the first transistor and a second terminal arranged to receive a second input signal; and a fourth capacitor having a first terminal coupled to the control terminal of the second transistor and a second terminal arranged to receive the second input signal.

An input buffer for an analog-to-digital converter, ADC, is provided. The input buffer is configured for receiving an input signal (V.sub.in) and for outputting an output signal (V.sub.out), and comprises an nMOS transistor and pMOS transistor. The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor connected between a gate of the nMOS transistor and a first biasing voltage potential (V.sub.21), and a second varactor connected between a gate of the pMOS transistor and a second biasing voltage potential (V.sub.22), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.