An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

Continuous time linear equalization devices are disclosed. A continuous time linear equalization device may include a first circuit including a first differential amplification element coupled to a first adjustable source degeneration element. The continuous time linear equalization device may also include a second circuit having an input coupled to an output of the first circuit and including a second differential amplification element coupled to a second adjustable source degeneration element. Systems are also disclosed.

A fully differential amplifier includes: an input stage comprising a first amplification circuit and a second amplification circuit, one of which is configured to generate a push signal and the other of which is configured to generate a pull signal, each by amplifying a differential input signal; an output stage for generating a differential output signal based on the push signal and the pull signal; and a feedback circuit for providing common mode feedback to the first amplification circuit based on the differential output signal, wherein the second amplification circuit may include a passive network for setting a common mode voltage of the push signal or the pull signal.

A differential amplifier circuit disclosed includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generates a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series to each other between drain and source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.

A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.

An integrated ultraviolet (UV) detector includes a silicon carbide (SiC) substrate, supporting metal oxide field effect transistors (MOSFETs), and PN Junction photodiodes. The MOSFET includes a first drain/source implant in the SiC substrate and a second drain/source implant in the SiC substrate. The P-N junction photodiodes include a blanket oxide over the silicon carbide substrate and the gate, an implant extending into the silicon carbide substrate, and an opening extending through the blanket oxide layer down to the silicon carbide substrate on one side of the gate of the P-N junction photodiode.

An amplifier includes an amplification circuit, an equalization circuit, an output circuit, a first gain adjusting circuit, and a second gain adjusting circuit. The amplification circuit changes voltage levels of first and second amplification nodes based on first and second input signals. The equalization circuit changes the voltage levels of the first and second amplification nodes. The output circuit generates an output signal based on the voltage levels of the first and second amplification nodes. The first gain adjusting circuit changes voltage levels applied to the first and second amplification nodes based on the voltage levels of the first and second amplification nodes and a first gain control signal. The second gain adjusting circuit changes a voltage level of the output signal based on a second gain control signal.

A circuit includes a first common-source amplifier configured to receive a first voltage at a first gate node and output a first current to a first drain node in accordance with a first source voltage at a first source node; a second common-source amplifier configured to receive a second voltage at a second gate node and output a second current to a second drain node in accordance with a second source voltage at a second source node; a first diode-connected device configured to couple the first source node to a DC (direct current) node; a second diode-connected device configured to couple the second source node to the DC node; and a source-degenerating resistor inserted between the first source node and the second source node.

A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals. Signal amplitude is detected with high precision, and detection reliability of a peak detecting circuit is improved.