An amplifier circuit having improved common mode rejection is provided. This can be achieved by estimating the common mode value of an input signal and using this to adjust a target common mode voltage at the output of the amplifier. This can help avoid the differential gain becoming modified by the common mode voltage.

An amplifier includes an amplifier circuit and a gain adjusting circuit. The amplifier circuit has a design gain and a real gain and is configured to output an output signal according to an input signal and the real gain. The gain adjusting circuit is coupled to the amplifier circuit and is configured to receive the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the real gain of the amplifier circuit, so that the real gain approach the design gain.

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Disclosed is a reconfigurable amplifier and an amplification method thereof, the amplifier includes an input selector, a first amplifying circuit, and a second amplifying circuit. The input selector is configured to select one of a voltage input and a current input based on a voltage measurement mode and a current measurement mode. The first amplifying circuit includes a first load element, and is configured to apply a voltage corresponding to the voltage input to the first load element in the voltage measurement mode and receive the current input in the current measurement mode and block a current flowing through the first load element. The second amplifying circuit is configured to mirror a current flowing through the first amplifying circuit in response to one of the voltage input and the current input and generate an output voltage based on the mirrored current.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.

A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

A waveform shaping circuit includes a first parallel circuit including a first capacitance element and a first resistance element coupled in parallel with each other, a positive pulse voltage being applied to a first terminal of the first capacitance element and a second terminal of the first resistance element, a first rectifier circuit disposed between a point of coupling between a third terminal of the first capacitance element and a fourth terminal of the first resistance element and an output terminal.

An integrated ultraviolet (UV) detector includes a silicon carbide (SiC) substrate, supporting metal oxide field effect transistors (MOSFETs), Schottky photodiodes, and PN Junction photodiodes. The MOSFET includes a first drain/source implant in the SiC substrate and a second drain/source implant in the SiC substrate. The Schottky photodiodes include another implant in the SiC substrate and a surface metal area configured to pass UV light.