An amplifier that amplifies a differential signal includes first and second input terminals for receiving two input signals; first and second diodes each including an anode and a cathode, the anodes being electrically connected to the first and second input terminals; first and second bias current sources being respectively electrically connected to the cathodes of the first and second diodes; an operational amplifier connected to the cathode of the first diode and the cathode of the second diode and configured to amplify a differential signal between signals generated at the cathodes of the first and second diodes; a capacitive element being electrically connected between an input and an output of the operational amplifier; and a differential amplifier provided between the operational amplifier and the first and second input terminals and configured to amplify the two input signals. The first and second bias current sources include a current mirror circuit.

A high speed internal hysteresis comparator is provided. Impedance supply units are disposed at control terminals of transistors of an active load of a differential amplifier of the high-speed hysteresis comparator, such that a gain when the transistors operate in an active region and a responding speed of the high-speed hysteresis comparator are increased.

The present application provides an apparatus for processing signals of a high-voltage loop, a detector, a battery device, and a vehicle. The apparatus includes a filter circuit connected to an element to be detected and configured to filter signals from the element to be detected; a differential amplification circuit connected to the filter circuit and configured to amplify the filtered signals; and a processor connected to the differential amplification circuit and configured to process the amplified signals.

Dual-supply analog circuitry for amplifying surface EMG (sEMG) signals is described. The circuitry includes a differential amplifier configured to be powered from dual-supply voltages. A positive input terminal of the differential amplifier is configured to be DC-coupled to a first sEMG electrode of a dry sEMG electrode pair and a negative input terminal of the differential amplifier is configured to be DC-coupled to a second sEMG electrode of the dry sEMG electrode pair.

The present technology relates to an amplifier, an audio signal output method, and an electronic device that can inhibit unintended sound output in a class D amplifier that changes a peak value of a PWM signal. The amplifier includes: a positive-side amplitude generating circuit configured to generate positive-side amplitude of an output PWM signal that is a PWM signal to be output outside an apparatus; a negative-side amplitude generating circuit configured to generate negative-side amplitude of the output PWM signal; and a feedback circuit configured to feed back a difference between the amplitude generated by the positive-side amplitude generating circuit and the amplitude generated by the negative-side amplitude generating circuit to the positive-side amplitude generating circuit and the negative-side amplitude generating circuit. The present technology is applicable, for example, to an amplifier or the like of an electronic device such as an audio player.

A two-stage fully-differential amplifier achieves a relatively high unity gain frequency yet has the current consumption by a second stage limited by a bias transistor that supplies current to an internal power supply rail. The internal power supply rail supplies power to two pairs of transistors for the second stage.

A programmable gain amplifier may include: (a) a differential amplifier having first and second input terminals and first and second output terminals, the differential amplifier providing an output signal of the programmable gain amplifier across the first and second output terminals of the differential amplifier; (b) a first set of one or more resistors coupling the first output terminal of the differential amplifier to the first input terminal of the differential amplifier; (c) a second set of one or more resistors coupling the first input terminal of the differential amplifier to a first input terminal of the programmable gain amplifier; and (d) a first set of one or more switches each connected in parallel with one or more resistors in the first or second set of resistors. The first set of switches may include two or more individually programmable switches. Each of the switches may be implemented by an input-signal independent switch disclosed herein.

A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.