A differential amplifier circuit disclosed includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generates a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series to each other between drain and source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.

A differential amplifier is provided. The differential amplifier includes: a differential input circuit, adjusting a second current and a third current flowing into the differential input circuit according to a first input voltage, a second input voltage, and a first current; a first current source circuit, generating the first current according to a first reference voltage; a current-mirror circuit, generating a fifth current according to a fourth current; a second current source circuit, generating a sixth current and a seventh current according to a second reference voltage; and an impedance circuit, coupled to the current-mirror circuit and a ground terminal, the differential amplifier having a low output voltage error.

A differential amplifier circuit includes a differential pair including a first field-effect transistor (FET) and a second FET, a first current source that generates a current which flows in the first FET and the second FET, and an output circuit that outputs an output voltage corresponding to a difference between a gate voltage of the first FET and a gate voltage of the second FET in accordance with an operation of the differential pair. A back gate of the first FET is connected to a gate of the first FET, and a back gate of the second FET is connected to a gate of the second FET. A first feedback voltage corresponding to the output voltage is input to the gate of the second FET.

A driving circuit includes a first differential amplifier, wherein the first differential amplifier includes: a delay adjustment circuit that generates a second differential signal by delaying a first differential signal in response to instantaneous voltage level of the first differential signal; a differential circuit that divides a source current into a first current and a second current in response to the second differential signal; and a first load resistor and a second load resistor that generate a positive phase component and a negative phase component of the differential output signal based on the first current and the second current, wherein a third differential amplifier operates in a non-saturated region when a voltage level of the first differential signal is in an input voltage range, and operates in a saturated region when the voltage level of the first differential signal is out of the input voltage range.

A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

A sensing system with an AC feedback to the non-signal and non-biased terminal of the transducer. An impedance element, such as two anti-parallel diodes, are provided at the amplifier input, and the amplifier gain is negative and has a size sufficient to ensure that the input on the one terminal does not exceed the forward voltage of the diode.

A differential amplifier circuit includes a differential pair including a first field-effect transistor (FET) and a second FET, a first current source that generates a current which flows in the first FET and the second FET, and an output circuit that outputs an output voltage corresponding to a difference between a gate voltage of the first FET and a gate voltage of the second FET in accordance with an operation of the differential pair. A back gate of the first FET is connected to a gate of the first FET, and a back gate of the second FET is connected to a gate of the second FET. A first feedback voltage corresponding to the output voltage is input to the gate of the second FET.

A multi-phase clock circuit includes a first delay circuit, a second delay circuit, a third delay circuit, a first clock mixer circuit, and a second clock mixer circuit. The first, second, and third delay circuits are coupled in series. The first clock mixer circuit includes a first input and a second input. The first input is coupled to an output of the first delay circuit. The second input is coupled to an output of the second delay circuit. The second clock mixer circuit also includes a first input and a second input. The first input of the second clock mixer circuit is coupled to an output of the second delay circuit. The second input of the second clock mixer circuit is coupled to an output of the third delay circuit.

Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.

A unity gain buffer provides an ON state in which the input signal is coupled to the output terminal and an OFF state in which the input signal is isolated from the output terminal. Multiple unity gain buffers may share the same load to form a voltage-mode maximum follower or a multiplexer.