An RF quasi circulator circuit is described herein. In accordance with one example of the disclosure the circuit includes a receive port, a transmit port and an antenna port as well as a differential amplifier stage having a first input, a second input and an output that is coupled to the receive port. The circuit further includes a first phase shifting element and a second phase shifting element. The first phase shifting element is coupled between the transmit port and the first input of the differential amplifier and the second phase shifting element is coupled between the transmit port and the second input of the differential amplifier. A tunable impedance is coupled to the differential amplifier, and the antenna port is coupled to the first input of the differential amplifier. The tunable impedance is controlled to tune the damping in a signal path from the transmit port to the receive port.

An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

A switching power stage for producing a load voltage may include a first processing path having a first output, a second processing path having a second output, a first plurality of switches comprising at least a first switch coupled between the first output and a first load terminal and a second switch coupled between the first output and the second load terminal, a second plurality of switches comprising at least a third switch coupled between the second output and the first load terminal and a fourth switch coupled between the second output and the second load terminal, and a controller configured to control switches in order to generate the load voltage as a function of an input signal such that one of the first switch and the second switch operates in a linear region of operation and one of the third switch and the fourth switch operates in a saturated region of operation for a predominance of a dynamic rage of the load voltage.

Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.

An integrated circuit includes a degeneration network configured to improve group delay across one or more variations, wherein the degeneration network includes a transimpedance amplifier with one or more degeneration inductors. The transimpedance amplifier further includes one or more transistors, and the one or more degeneration inductors are connected after at least one emitter of the one or more transistors.

A switching power stage for producing a load voltage may include a first processing path having a first output, a second processing path having a second output, a first plurality of switches comprising at least a first switch coupled between the first output and a first load terminal and a second switch coupled between the first output and the second load terminal, a second plurality of switches comprising at least a third switch coupled between the second output and the first load terminal and a fourth switch coupled between the second output and the second load terminal, and a controller configured to control switches in order to generate the load voltage as a function of an input signal such that one of the first switch and the second switch operates in a linear region of operation and one of the third switch and the fourth switch operates in a saturated region of operation for a predominance of a dynamic rage of the load voltage.

A switching power stage for producing a load voltage at a load output of the switching power stage, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first and the second load voltages, that may include: a power converter comprising a power inductor and a plurality of switches, wherein the power converter is configured to drive a power converter output terminal; a linear amplifier configured to drive a linear amplifier output terminal; and a controller for controlling the plurality of switches and the linear amplifier in order to generate the load voltage as a function of an input signal to the controller such that energy delivered to the load output is supplied predominantly by the power converter.

To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground.