A system includes an amplification circuit and offset calibration circuit. The amplification circuit includes a modulation circuit operable to modulate a received signal, an amplifier operable to amplify the modulated signal, and a modulation circuit operable to demodulate the amplified signal. The offset calibration circuit includes a logic circuit operable to set a control signal and adjust the control signal based on an output of the amplification circuit, where the output is based on the demodulated signal, and a compensation signal generator operable to generate a compensation signal based on the control signal to compensate for an offset associated with the amplification circuit, and apply the compensation signal on the amplification circuit to adjust the output of the amplification circuit. The offset calibration circuit in conjunction with the application circuit reduces flicker, offset, and offset drift, and also suppresses the upmodulate ripple due to chopping.

Provided is a multistage amplifier that can achieve both utilizing in a broad bandwidth and suppressing gain reduction. The multistage amplifier includes a plurality of differential amplifiers which are connected in series; and a direct-current component limiter that cuts off a direct-current component of input signals, in which the direct-current component limiter is disposed between the plurality of differential amplifiers, and in which a transistor size of a first differential amplifier which is disposed immediately after the direct-current component limiter is equal to or greater than a transistor size of a second differential amplifier which is disposed two stages before the direct-current component limiter.

An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.

Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.

An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.

A differential amplifier includes an amplifying stage that outputs an output signal by amplifying an input signal with a gain set by a control signal, and an adjusting stage that stabilizes a DC level of the output signal. The amplifying stage includes a first source supplying a first current, and a load, and determines a ratio of a current flowing through the load to the first current depending on the input signal and the control signal, and generates the output signal from a voltage drop of the load. The adjusting stage includes a second source supplying a second current, and a monitor resistor, and generates a monitor current divided from the second current by the ratio, and duplicates the DC level as a voltage drop of the monitor resistor caused by the monitor current, and controls the first current source and the second current source depending on the DC level.

An offset-cancellation circuit having a first amplification stage with a gain of the first amplification stage and configured to receive an offset voltage of a first amplifier. A storage element is configured to be coupled to and decoupled from the first amplification stage and configured to store a potential difference output by the first amplification stage. The potential difference is determined by the offset voltage of the first amplifier and the gain of the first amplification stage. A second amplification stage is coupled to the storage element and configured to receive the potential difference from the storage element when the storage element is decoupled from the first amplification stage and configured to deliver an offset-cancellation current. The offset-cancellation current is determined by the potential difference and a gain of the second amplification stage.

An input stage circuit for an operational amplifier includes first and second differential pairs connected in parallel between positive and negative input terminals. Each differential pair comprises a pair of transistors that are intentionally and systematically mismatched. The mismatching of each transistor pair creates a pre-trim input offset voltage for the circuit. However, a unique current is utilized to bias each of the first and second differential pairs. By adjusting the differential between the bias currents, a composite input offset voltage is created that combines with the pre-trim input offset voltage to yield a total input offset voltage for the circuit that approaches zero. Additionally, adjusting the differential between the bias currents simultaneously trims the temperature coefficient of the total input offset voltage to zero while using limited power and producing minimal noise.

Disclosed is a circuit having a differential stage comprising a pair or transistors. The transistors are biased by respective bias transistors. Each bias transistor has a respective feedback network configured to reduce transconductance of the bias transistor, to increase a gain of the differential stage.