According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.

A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.

According to one embodiment, an apparatus comprises a differential signaling bus, a tristate transmitter connected with the differential signaling bus, the tristate transmitter configured to provide a signal on the differential signaling bus responsive to a corresponding control signal, a receiver, a pair of differential inputs of the receiver connected with the differential signaling bus and configured to receive the signal from the differential signaling bus, and a termination circuit configured to couple a first differential input of the pair of differential inputs to a first voltage source and to couple a second differential input of the pair of differential inputs to a second voltage source, wherein the first and second voltage sources have different voltage levels.

An integrated circuit comprises an ADC including a first track-and-hold amplifier and a timing generator configured to generate a clock signal for controlling the ADC. The timing generator comprises a quadrature filter responsive to a differential input signal for generating a differential quadrature (I/Q) output signal. The timing generator further comprises at least one first vector sum circuit operatively coupled or connected to an output of the quadrature filter and configured to weight and sum components of the differential I/Q output signal for generating a clock signal having a desired delay.

An amplifier system includes a Class-D power amplifier integrated circuit (IC) that is nested inside a feedback loop of a low noise differential operational amplifier (op-amp).

To provide a variable gain amplifier capable of correcting a DC offset voltage through simpler control even when a gain thereof is changed. A differential output type variable gain amplifier is equipped with a first voltage correction unit coupled to a preceding stage of a variable gain amplifier circuit and for outputting a first correction voltage to correct a potential difference generated between a first conductor provided with a first input resistor and a second conductor provided with a second input resistor, and a second voltage correction unit coupled to a subsequent stage of the variable gain amplifier circuit and for correcting a differential output. A control unit is configured to control the first correction voltage and a correction amount of a potential difference by the second voltage correction unit and thereby attenuate a DC offset voltage included in the differential output.

A communication circuit may include mixers configured to generate voltage mode outputs. The communication circuit may further include voltage nodes configured to sum the voltage mode outputs produced by the mixers to generate intermediate voltage mode signals. The communication circuit may further include transconductors configured to convert the intermediate voltage mode signals to intermediate current mode signals. The communication circuit may further include at least one current node configured to sum the intermediate current mode signals to generate at least one mixer output signal.

An amplifier includes a differential amplification block suitable for receiving and amplifying a first differential input signal and a second differential input signal; an output block suitable for determining an output signal according to a state of amplified signals outputted from the differential amplification block; and an output range restriction block suitable for controlling an output range of the output signal outputted from the output block based on a maximum clamping signal and a minimum clamping signal.

A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.

A CMOS channel select filter for DVB-H direct-conversion receives based on a transresistance amplifier (TRA) is disclosed. The channel select filter includes a fully differential transresistance amplifier (FDTRA) configured to change an input current at each differential input terminal to a voltage at each differential output terminal based on an impedance at a corresponding differential impedance terminal. The channel select filter also includes two feedback resistors, each having one end connected to a respective differential output terminal of the FDTRA and having another end connected to the node, two first capacitors, each connected between ground and the node, and two second capacitors, each connected between ground and a respective differential impedance terminal.