A signal amplification method includes receiving, from a capacitive sensor, a first input signal by a first control terminal of a first transistor, and a second input signal by a first control terminal of a second transistor. The method also includes producing a first output signal, including amplifying a first signal at a first load path terminal of the first transistor using a first inverting amplifier having an output coupled to a resistance network, and producing a second output signal, including amplifying a second signal at a first load path terminal of the second transistor using a second inverting amplifier having an output coupled to the resistance network. The method also includes feeding back the first and second output signal to a second load path terminal of the first transistor and to a second load path terminal of the second transistor via the resistance network according to a pre-determined fraction.

A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.

A readout circuit has a first transistor which have a first terminal, a second terminal, and a control terminal, a second transistor having a first terminal, a second terminal, and a control terminal, a first variable resistance having a first terminal connected to a first reference voltage line, and a second terminal connected to the first terminal of the first transistor, a first resistance having a first terminal connected to the first reference voltage line, and a second terminal connected to the first terminal of the second transistor, a second resistance having a first terminal connected to the second terminal of the first transistor, and a second terminal connected to a second reference voltage line, and a second variable resistance which has a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second reference voltage line.

A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.

In one implementation, a circuit can include a reference pin and an operational amplifier that can include an output pin, an inverting input pin and a non-inverting input pin. The inverting input pin can be electrically coupled to the output pin via a first impedance and to the reference pin via a second impedance. The non-inverting input pin can be electrically coupled to the reference pin via a third impedance and can be configured to receive a detection signal. The reference pin can be configured to receive a detection reference signal associated with the detection signal.

The application discloses a tuner and a method for tuning a signal. The tuner comprises: a sampling module, the sampling module being configured to receive an input signal and a set of control signals, sample the input signal under the control of the set of control signals and generate a sample signal; wherein each of the set of control signals has a control period equal to (N*T.sub.VCO), and the control periods of the set of control signals synchronize with each other; a set of weighting modules, wherein each of the set of weighting modules is configured to receive the set of sample signals and weight the received sample signals with a group of weighting factors to generate a group of weighted signals; and one or more summing modules, each summing module being configured to receive one group of weighted signals generated by one of the set of weighting modules and sum the group of weighted signals to output an output signal, wherein the output signal is the input signal being shifted by a predefined frequency f.sub.VCO*m.sub.k/N.

A receiver circuit may be provided. The receiver circuit may include a first duty cycle adjuster configured to correct a duty cycle of a first output signal pair. The receiver circuit may include a second duty cycle adjuster configured to correct a duty cycle of a second output signal pair, based on the first output signal pair, after the first duty cycle adjuster performs a correction on the duty cycle of the first output signal pair.

An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.

A device for measuring current by means of integration, includes a first operational amplifier connected as an integrator, and a second operational amplifier connected as an original current generator which can compensate for leakage current in the circuit measurement state and reset the Q0 charge of the integration capacitor in the reset state.