A circuit comprises a sensing resistor with a resistance Rs, a first amplifier circuit with a first gain factor G, a second amplifier circuit with a second gain factor (1/A), a third amplifier circuit, a current mirror, a buffer, and a peak voltage detector. The first amplifier circuit is coupled to the sensing resistor at a first node and a second node and to the second amplifier circuit, which is further coupled to the current mirror. The buffer is coupled to the current mirror and to the third amplifier circuit, which is further coupled to the peak voltage detector and configured to receive a voltage across a load and a voltage on a ground node. In some implementations, the load is a speaker. In some implementations, a filter is coupled between the first and the second amplifier circuits.

An amplifier circuit includes: an amplifier; and a bias circuit that controls an operation point of the amplifier. The amplifier includes: a load resistor; a differential transistor pair electrically coupled to the load resistor; and a tail transistor electrically coupled to the differential transistor pair. The bias circuit includes: a voltage generator circuit that generates a reference voltage corresponding to a sum of a threshold voltage of a transistor in the differential transistor pair and a saturation drain voltage of the tail transistor; and a current generator circuit that generates a reference current that is proportional to a difference between a power supply voltage of the amplifier circuit and the reference voltage by using a reference resistor. The current generator circuit is electrically coupled to the amplifier such that a tail current that flows through the tail transistor is proportional to the reference current.

An amplifier device includes an amplifying unit, a bias module, an impedance unit and an adjusting module. The amplifying unit has a first end coupled to a voltage source and used for outputting an output signal amplified by the amplifying unit, a second end used for receiving an input signal, and a third end coupled to a first reference potential terminal. The bias module is coupled to the second end of the amplifying unit, and provides a bias voltage to the amplifying unit and adjusts linearity of the amplifier device according to a source voltage from the voltage source. The impedance unit is coupled to the bias module and used to receive a control voltage to adjust an impedance value of the impedance unit. The adjusting module is used to output the control voltage to the impedance unit according to the source voltage and a reference voltage.

Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

An industrial control I/O module for interfacing with industrial control equipment, such as sensors and actuators, can be configured to dynamically provide differing resistances in each channel as may be required for reliably achieving particular modes of operation in the channel. Providing differing resistances in such channels flexibly allows different modes in the channel to provide universal I/O capability. Modes of operation could include, for example, digital output, digital input, analog output, analog input and the like, in the same channel, but at different times. In one aspect, a processor or voltage divider can be used to control an amplifier, with feedback, driving a transistor in a channel to dynamically adjust resistance in the channel by selectively biasing the transistor to achieve a resistance in the channel suitable for the selected mode.

A display driver includes an operational amplifier, a D/A conversion circuit, a resistance circuit, and a resistance element. The D/A conversion circuit includes first and second variable resistance circuits including one end to which first and second voltages are input and another end connected to an inverting input node. The resistance circuit is provided between the inverting input node and an output node. The resistor is provided between the output node and the inverting input node. A resistance value of the first variable resistance circuit is set based on upper bit data of display data. A resistance value of the second variable resistance circuit is set based on lower bit data of the display data.

A display driver includes a D/A converter circuit for outputting a gradation voltage, and an amplifier circuit that is input with a gradation voltage at an input node. The amplifier circuit includes an operational amplifier, resistance provided between the input node and a node, resistance provided between a node and an output node of the operational amplifier, and an adjustment resistance circuit. The adjustment resistance circuit adjusts a first adjustment resistance value, that is a resistance value between a node and an inverting input node of the operational amplifier, and a second adjustment resistance value, that is a resistance value between the node and the inverting input node.

An apparatus is provided for monitoring heart rate. The apparatus comprises various components to effectively reduce photodiode capacitance. The apparatus includes: an amplifier; a first current source; a first pair of resistors coupled to the first current source and the amplifier; a pair of devices coupled to the first pair of resistors; a photo-diode coupled to the pair of devices; a second pair of resistors coupled to the pair of devices and the photo-diode; and a second current source coupled to the second pair of resistors.

An apparatus includes a plurality of transmitter channels and a plurality of feedback networks. Each of the plurality of transmitter channels may be coupled to a respective antenna element in a respective group of antenna elements of a phased array antenna. Each of the transmitter channels generally comprises a power amplifier circuit configured to drive the respective antenna element in the respective group of antenna elements to produce and steer a radio-frequency beam. Each of the plurality of feedback networks may be coupled between an output and an input of a respective power amplifier circuit of a respective transmitter channel. Each of the feedback networks generally comprises a resistor and a capacitor connected in series. The respective power amplifier circuit with the feedback network generally maintains a power matching condition with load variation associated with performing beam steering of the radio-frequency beam using the antenna elements of the phased array antenna.