Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code is by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

A receiving circuit includes a first capacitor connected to a first signal line, a second capacitor connected to a second signal line. A first bias control circuit may convert a common mode voltage of a first received signal provided through the first capacitor to a first voltage level to output a first biased signal. A second bias control circuit may convert a common mode voltage of a second received signal provided through the second capacitor to a second voltage level to output a second biased signal. A balance compensation circuit may receive the first biased signal and the second biased signal, compensate for an offset voltage of the first biased signal based on the second biased signal, and compensate for an offset voltage of the second biased signal based on the first biased signal to output a first differential signal and a second differential signal.

Power amplifier (PA) output memory neutralization is disclosed, using baseband input/output (I/O) capacitance current compensation. Radio frequency (RF) PAs experience I/O memory effects when used with envelope tracking supply modulation schemes. Envelope tracking supply modulation results in a nonlinear variation of the I/O capacitance. Traditional approaches compensate for such effects with a current provided by a bias circuit which is band-limited. This results in memory effects which distort the amplified signal, becoming more significant as the modulation bandwidth increases. An RF communications system according to embodiments disclosed herein mitigates such memory effects by compensating for the non-linear effect of the I/O capacitance in an RF PA.

Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Apparatuses and techniques are described for calibrating a negative voltage source. A ground voltage is applied to a multi-stage amplifier from the negative voltage source while an offset voltage measurement (OVM) is made at the output of the multi-stage amplifier. The OVM is recorded and subsequently used by a calibration circuit when the negative voltage source applies a range of negative voltages to the input of the multiple stage amplifier. The calibration circuit subtracts the OVM from measurements obtained at the output of the multi-stage amplifier to obtain corrected measurements, and uses the corrected measurements to calibrate the negative voltage source, e.g., by adjusting a relationship between digital values input to the negative voltage source and the output voltages.

Provided is a compensation circuit for an operational amplifier including a primary pole. The compensation circuit includes: a control circuit; and a compensation capacitor including a first terminal connected to the primary pole, and a second terminal connected to an output terminal of the control circuit. The control circuit includes: a pull-up module including a control terminal connected to a second control signal terminal, an input terminal connected to an input power supply, and an output terminal connected to a first control node being the output terminal of the control circuit; a pull-down module including a control terminal connected to a first control signal terminal, and an output terminal connected to ground; and an input transistor including a control terminal connected to the primary pole, an input terminal connected to a first control node, and an output terminal connected to an input terminal of the pull-down module.

A data storage apparatus includes storage and a controller configured to control the storage in response to a request from a host. The controller includes an internal voltage trimming circuit which includes: an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage; a transition detection circuit configured to output a detection signal according to level transition of the comparison signal; a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the storage.

Embodiments of the present application provide a readout circuit, an image sensor and an electronic device, which could effectively reduce an area and power consumption of the image sensor. The readout circuit includes a plurality of capacitors, a switch circuit and an output circuit; where the plurality of capacitors are connected to the output circuit through the switch circuit; the plurality of capacitors are configured to store output signals of a plurality of pixel circuits, respectively; and the output circuit is configured to output signals stored by the plurality of capacitors through the switch circuit one-by-one.