An apparatus for detecting capacitance, an electronic device and an apparatus for detecting a force are disclosed. The apparatus for detecting capacitance includes: a signal driving circuit (110), configured to periodically charge and discharge at least one capacitor to be detected; a conversion circuit (120), configured to convert a capacitance signal of the at least one capacitor to be detected into a voltage signal; and a cancellation circuit (130), configured to cancel initial capacitance of the at least one capacitor to be detected, so that the voltage signal is associated with a capacitance change of the at least one capacitor to be detected. The apparatus for detecting capacitance could improve the anti-interference performance and improve the accuracy of capacitance detection.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation. Therefore, a number of cascade MOSs of the low voltage inverter-based amplifier is two, and the low voltage inverter-based amplifier can be normally operated under the low supply voltage.

A circuit device includes a selector to which first to n-th voltages are input, an A/D converter circuit to which output voltages of the selector are input as input voltages, and first to n-th quantization error hold circuits that hold charges corresponding to quantization errors in A/D conversion of the first to n-th voltages. The A/D converter circuit performs A/D conversion of an input voltage by a successive approximation operation using a charge redistribution type D/A converter circuit and performs k-th A/D conversion on an i-th voltage by using a charge held in an i-th quantization error hold circuit in (k1)th A/D conversion of the i-th voltage to output A/D conversion result data DOUT in which the quantization error is noise-shaped.

An aerosol delivery device is provided. The aerosol delivery device includes terminals configured to connect a power source to the aerosol delivery device and a heating element configured to convert electricity to heat and thereby vaporize components of an aerosol precursor composition. The aerosol delivery device also includes a boost converter configured to step up voltage from the power source to a higher voltage and an inverter configured to convert the higher voltage to a complementary negative voltage. The aerosol delivery device further includes at least one non-inverting amplifier circuit that includes an operational amplifier configured to receive the voltage from the power source as an input voltage, and receive the higher voltage and the complementary negative voltage as supply voltages. The at least one non-inverting amplifier circuit is configured to amplify the input voltage to an output voltage, and provide a continuous output current.

A high-to-low voltage interface circuit includes a differential circuit stage with a differential amplifier circuit having inverting and non-inverting inputs coupled to first and second input pads as well as a differential output having first and second output nodes. A pair of bias amplifier stages sensitive to the common mode voltage of the differential amplifier circuit are arranged in first and second current mirror paths from the first and second input pads to the inverting/non-inverting inputs of the differential amplifier circuit, respectively. The bias amplifier stages are configured to maintain the first input pad and the second input pad of the differential circuit stage at the common mode voltage.

A sensing circuit for an organic light-emitting diode driver includes a sample and hold circuit and a gain amplifier. The sample and hold circuit is configured to sample a sensing signal received via an input terminal. The gain amplifier is coupled to the sample and hold circuit. The sample and hold circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch and a fourth switch. The first capacitor is coupled between the input terminal and the gain amplifier. The second capacitor is coupled between a reference terminal and the gain amplifier. The first switch is connected between the first capacitor and the input terminal. The second switch is connected between the second capacitor and the reference terminal. The third switch is connected between the first capacitor and the gain amplifier. The fourth switch is connected between the second capacitor and the gain amplifier.

A frequency-modulated continuous-wave radar system includes a waveform generator, a delta-sigma modulation circuit, a voltage controlled oscillator, a frequency divider circuit, a control circuit, an injection locked oscillator, a power amplifier circuit, a first power detection circuit, a second power detection circuit, a third power detection circuit, and a calibration engine circuit. The waveform generator, the delta-sigma modulation circuit, the voltage controlled oscillator, the frequency divider circuit, and the control circuit form a phase locked loop. The calibration engine circuit is coupled to the delta-sigma modulation circuit, the voltage controlled oscillator, the injection locked oscillator, the power amplifier circuit, the first power detection circuit, the second power detection circuit, and the third power detection circuit for adjusting frequency gains of the voltage controlled oscillator, the injection locked oscillator, and the power amplifier circuit to approach wideband flatness frequency responses.

A power amplifier circuit includes a power amplifier that amplifies the power of a high frequency signal, a power amplifier temperature detector circuit that includes a temperature detection element, the temperature detection element being thermally coupled with the power amplifier, a bias control signal generator circuit that generates a bias control signal for the power amplifier based on a temperature detection signal outputted from the power amplifier temperature detector circuit, and a regulator circuit that stabilizes the temperature detection signal. The power amplifier, the power amplifier temperature detector circuit, and the regulator circuit are formed in a first integrated circuit, and the bias control signal generator circuit is formed in a second integrated circuit. The substrate material (for example, GaAs) of the first integrated circuit has a higher cutoff frequency than the substrate material (for example, SOI) of the second integrated circuit.