A photoelectric conversion device is provided. The device comprises a light receiving element, first and second transimpedance amplifiers configured to receive a signal of the light receiving element and output a voltage, a differential operation amplifier configured to perform a differential amplification for outputs of the first and second transimpedance amplifiers and a switching unit. The switching unit includes an output switching unit configured to switch connections between a first state where the light receiving element and the first transimpedance amplifier are connected and a second state where the light receiving element and the second transimpedance amplifier are connected, and a capacitance adjusting unit connected to an input terminal of each of the first and second transimpedance amplifiers and configured to adjust a capacitance value of the first and transimpedance amplifier and/or a capacitance value of the second transimpedance amplifier.

A semiconductor device includes a magnetic switch provided on a semiconductor substrate. The magnetic switch includes: a Hall element, first and second power supply terminals; a current source driving the Hall element; a switch circuit switching a differential output voltage supplied from two electrodes of the Hall element to a first or second state based on a control signal supplied from a control terminal; an amplifier amplifying a signal from the switch circuit; a reference voltage circuit generating a reference voltage based on a reference common mode voltage and a control signal; a comparator receiving an output signal of the amplifier and the reference voltage; and a latch circuit latching an output voltage of the comparator. The reference voltage of the reference voltage circuit is controlled by switching from a reference value to a voltage with a high or low adjustment value according to the output voltage of the comparator.

A correlated double sampling integrating circuit is provided. The circuit includes: a sampling and holding module, an energy storage unit and a feedback module. The sampling and holding module is configured to perform sampling and holding for different input signals. The energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals, and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to keep consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. The correlated double sampling integrating circuit reduces noise, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations.

In some embodiments, a circuit for use in devices involving digital-to-analog conversion of signals includes: a capacitive digital-to-analog converter array and an amplifier. The capacitive digital-to-analog converter includes an input port for receiving a digital input signal and an output port. The amplifier includes capacitive feedback loops that include a first capacitor coupling the output of the amplifier with the input of the amplifier and a second capacitor coupled to the output port of the digital-to-analog converter array at the input of the amplifier. The circuit further includes a set of switches that include a first switch and a second switch coupled with opposed ends of the second capacitor at the input and at the output of the amplifier, respectively.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

A voltage detection device comprises a voltage detection circuit, which is a fully-differential type and a control circuit for controlling an operation of the voltage detection circuit. The voltage detection circuit includes a switched capacitor circuit, a differential amplifier, a common mode feedback circuit for controlling a common mode level of an output voltage of the differential amplifier and a bias circuit for supplying biases to the differential amplifier and the common mode feedback circuit. The control circuit controls the voltage detection circuit to execute intermittently a detection operation for detecting the voltage. The control circuit controls the voltage detection circuit to execute a pseudo operation of an execution period, which is shorter than that of the detection operation, during a transition period from a stop state, in which no detection operation is executed, to the operation state, in which the detection operation is executed.

A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.

There is provided a phase-switch-equipped variable amplification device including a switch including one input port and two output ports and configured to output a single-ended signal input to the one input port into one of the two output ports, a first converter coupled to the two output ports of the switch and configured to convert the single-ended signal output from the switch into a pair of differential signals having phases different from each other by 180-degree and invert phases of the pair of differential signals in response to a switching operation at the switch, a variable amplifier configured to amplify the pair of differential signals in accordance with a control voltage, and a second converter configured to convert the pair of differential signals amplified by the variable amplifier into a single-ended signal.

A correlated double sampling integrating circuit is provided. The circuit includes: a sampling and holding module, an energy storage unit and a feedback module. The sampling and holding module is configured to perform sampling and holding for different input signals. The energy storage unit is configured to store charges corresponding to the input signals upon the sampling and holding to generate node signals, and the feedback module is configured to form a negative feedback loop with the energy storage unit to control node signals at an integrating stage to keep consistent with node signals at a resetting stage and prevent output jump of the correlated double sampling integrating circuit. The correlated double sampling integrating circuit reduces noise, and prevents or weakens output jump of the correlated double sampling integrating circuit caused by the increase of the count of integrations.

In some embodiments, a circuit for use in devices involving digital-to-analog conversion of signals includes: a capacitive digital-to-analog converter array and an amplifier. The capacitive digital-to-analog converter includes an input port for receiving a digital input signal and an output port. The amplifier includes capacitive feedback loops that include a first capacitor coupling the output of the amplifier with the input of the amplifier and a second capacitor coupled to the output port of the digital-to-analog converter array at the input of the amplifier. The circuit further includes a set of switches that include a first switch and a second switch coupled with opposed ends of the second capacitor at the input and at the output of the amplifier, respectively.