Technologies relating to RRAM-based crossbar array circuits and more specifically to reducing row switch resistance error of in crossbar array circuits are disclosed. An example apparatus includes: a first Op-amp including a first inverting Op-amp input, a first non-inverting Op-amp input, and a first Op-amp output; a row switch device including a row switch input and a row switch output; a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire. The row switch input is connected to the first Op-amp output; the row switch output is connected to the first inverting Op-amp input; and the row switch output is connected to the row wire.

A pixel circuit includes a differential amplifier. The differential amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The differential amplifier includes an input differential pair including first and second NMOS transistors, a current mirror pair including PMOS transistors, and a constant current source including a fifth NMOS transistor. A threshold voltage of each of the first and second NMOS transistors is higher than a threshold voltage of the fifth NMOS transistor. Further, the threshold voltage of each of the first and second NMOS transistors is higher than a threshold voltage of another NMOS transistor.

Technologies relating to RRAM-based crossbar array circuits and more specifically to reducing row switch resistance error of in crossbar array circuits are disclosed. An example apparatus includes: a first Op-amp including a first inverting Op-amp input, a first non-inverting Op-amp input, and a first Op-amp output; a row switch device including a row switch input and a row switch output; a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire. The row switch input is connected to the first Op-amp output; the row switch output is connected to the first inverting Op-amp input; and the row switch output is connected to the row wire.

A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.

An input/output circuit may include an input circuit, an amplifier circuit and a precharging circuit. The input circuit may load differential input data to setup nodes based on a data strobe clock. The amplifier circuit may compare and amplify the data that is loaded to the setup nodes and configured to output the amplified data. The precharging circuit may precharge the setup nodes based on the data strobe clock and the differential input data.

A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.

An amplifier comprising a differential amplifier configured to be provide a comparator function, and a gain trimming circuit is electrically configured to provide gain trimming using a T-network comprising a varistor element. In addition, a method of trimming the gain of a differential amplifier, comprising the steps of a first step, (a) providing the differential amplifier comprising resistors in both of its paths, a second step, (b) providing a varistor in a T-network between both said paths; and lastly, a third step, (c) trimming the gain of the differential amplifier by adjusting the varistor's resistance.

An attenuation circuit with stages having constant dB steps between stages is provided. The attenuation circuit can be configured as a ladder network using resistors having three different values. A first resistor can be connected between the last stage of the attenuation circuit and ground and have a first predetermined resistance. One or more second resistors can be connected in each stage and have a second predetermined resistance based on the first predetermined resistance and the dB step between stages. One or more third resistors can be connected in parallel to the first resistor for the remaining stages and have a third predetermined resistance based on the first predetermined resistance and the dB step between stages.

Methods, systems, and devices for enabling the use of SIP subsystems to make a configurable system with desired characteristics and features are provided. A configurable system's unique interconnecting scheme creates appropriate connections between the SIP components and/or subsystems.

An amplifier comprising a differential amplifier configured to be provide a comparator function, and a gain trimming circuit is electrically configured to provide gain trimming using a T-network comprising a varistor element. In addition, a method of trimming the gain of a differential amplifier, comprising the steps of a first step, (a) providing the differential amplifier comprising resistors in both of its paths, a second step, (b) providing a varistor in a T-network between both said paths; and lastly, a third step, (c) trimming the gain of the differential amplifier by adjusting the varistor's resistance.