A power amplifier circuit includes a differential amplifier circuit configured to amplify a radio-frequency signal, a transformer disposed on an output side with respect to the differential amplifier circuit and including a primary winding and a secondary winding, and a dispersion circuit coupled to a midpoint of the primary winding of the transformer and configured to operate as an adjustment circuit. The dispersion circuit is configured to adjust, based on a supply voltage controlled in accordance with the envelope of the radio-frequency signal, a bias (bias current or bias voltage) to be supplied to the differential amplifier circuit.

An operational amplifier operates in the entire voltage range of supplied first and second voltages as an input and output range. An active load is formed with a field-effect transistor of a first conductivity type. First and second differential pairs are formed with a field-effect transistor of a second conductivity type. The first differential pair is configured such that differential amplification is possible when an input voltage is the second voltage, and the second differential pair is configured such that differential amplification is possible when the input voltage is the first voltage. A selection circuit selectively connects one of the first and second differential pairs to the active load through a differential node in accordance with the input voltage.

An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.

An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

An image sensor and electronic apparatus comprise a pixel circuit configured to generate an analog signal; a vertical signal line configured to convey the analog signal from the pixel circuit; an analog amplifier circuit configured to receive the analog signal via the vertical signal line and generate an amplified signal; and a tail current boost circuit configured to modify an instantaneous gain bandwidth product of the analog amplifier circuit by temporarily modifying a tail current of the analog amplifier circuit.

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.

A circuit includes a first current source of a first type, a common-source gain device, a load, a second current source of a second type, a first common-mode network, and a second common-mode network. The first current source pulls a first bias current from a source node according to a first bias voltage. The common-source gain device receives an input voltage and outputs an output current to a drain node according to the first bias current. The load provides a termination to the drain node. The second current source outputs a second bias current to the drain node according to a second bias voltage. The first common-mode network outputs the first bias voltage according to a constant-gm reference current. The second common-mode network outputs the second bias voltage according to a difference between a mean voltage at the drain node and a scaled reference voltage.