In an embodiment, an electronic device includes a first amplifier having a non-inverting input configured to receive a reference voltage and an inverting input coupled to a first output node, where the first amplifier is configured to produce a first output voltage at the first output node. The electronic device also includes a second amplifier having a non-inverting input coupled to a ground reference level, and an inverting input coupled to the first output node via a first resistor and to a second output node via a second resistor, where the second amplifier is configured to produce a second output voltage at the second output node.

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal.

A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

A power supply in a test and measurement device includes a stimulus having an output coupled to an amplifier in which an output signal from the stimulus controls an output level of the amplifier. The stimulus may include a Digital to Analog Converter. A measurement circuit detects the output level of the amplifier. The power supply includes an overpulse generator that can be structured to accept a desired amplifier output level, overdrive the stimulus at a first level for a first time period, and drive the stimulus at a second level for a second time period. The measurement circuit determines when the overpulse generator switches from driving the stimulus at the first level to driving the stimulus at the second level. The time period for driving the stimulus at the second level starts as the actual amplifier output level approaches the desired amplifier output level.

A slew rate acceleration circuit in a buffer circuit, is configured at least to detect a current flowing through a load stage of the buffer circuit, compare a value of the detected current with a reference value, and supply an adjusting driving voltage to an output stage of the buffer circuit based on results of the comparison for increasing a slew rate of the buffer circuit.

Disclosed is an amplifier having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a slew rate improvement circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a first slew rate improvement circuit, and a second slew rate improvement circuit.

Disclosed is an amplifier capable of minimizing short-circuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

An output buffer circuit includes an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and on a compensation current, a slew rate compensating circuit configured to generate the compensation current to increase a slew rate of the amplifier output voltage signal based on a difference between the input voltage signal and a feedback voltage signal, an output path circuit connected between the operational amplifier and an output pad, the output path circuit configured to transfer the amplifier output voltage signal to generate a pad output voltage signal through the output pad, and a feedback path circuit, the feedback path circuit connected between the slew rate compensating circuit and a feedback input node that is on the output path circuit, the feedback path circuit configured to generate the feedback voltage signal.