An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.

A buffer amplifier circuit includes a buffer amplifier including a first differential amplifier having a first active load and a second differential amplifier having a second active load and a feedback circuit configured to feed an output signal of an output terminal of the buffer amplifier back to one of the first and second active loads using differential switch signals and an input signal of the buffer amplifier to enhance a slew rate of the output signal.

An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.

A semiconductor device includes a low power fast differential transconductor, which provides an output current as a function of a difference between a reference potential input and a feedback potential input. The transconductance increases as an absolute value of the difference between the reference potential and the feedback potential increases. The transconductor includes a reference input stage to receive the reference potential and a reference load coupled in series with the reference input stage. The transconductor includes a feedback input stage to receive the feedback potential and a feedback load coupled in series with the feedback input stage. The transconductor further includes a current limiting component that is configured to control a total current through the reference input stage and the feedback input stage. The transconductor includes a negative feedback path from the reference load to the current limiting component, that compensates for changes in the total current due to differences between the reference potential and the feedback potential.

An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.

An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.

An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.

An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.

A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.