A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.

An output stage of a buffer or an amplifier connected to a switched capacitive load can operate in two phases to perform precharging and fine settling. The precharging and fine settling phases can be synchronized to the switching phases of the switched capacitive load connected to the amplifier. During the precharging phase, the output stage can be disconnected from the prior stages of the amplifier, and the output node of the amplifier can be connected to the switched capacitive load to precharge the capacitive load with the voltage already stored in the output stage. During the fine settling phase, the output stage can be reconnected to the prior stages of the amplifier, and the amplifier nodes can settle and get ready for sampling, which can occur at the end of the fine settling phase.

Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.

A heterojunction bipolar transistor (HBT) hybrid type RF (radio frequency) power amplifier includes a first device including an input terminal for receiving an RF signal, a pre-driver stage for amplifying the received RF signal, and an output terminal, the input terminal, the pre-driver stage and the output terminal being disposed in or over a first substrate; and a second device having a main stage having an HBT amplifier circuit disposed in or over a second substrate to further amplify the RF signal amplified by the pre-driver stage. The RF signal further amplified by the main stage is output through the output terminal of the first device.

An integrated circuit device includes a digital-to-analog converter with multiple bit slices, each bit slice having a differential pair of driver transistors. A driver circuit includes the differential pairs of driver transistors, multiple series cascode transistors, and current bleed paths to modify drain-to-source currents in the various cascode transistors. Additional embodiments include series peaking circuits, back termination networks, and neutralization capacitors. Other embodiments are disclosed.