A current monitoring circuit includes: an output terminal configured to be coupled to a controller; an inverter having an output coupled to the output terminal; a first transconductance amplifier having first and second inputs configured to be coupled across a sense resistive element, and an output coupled to an input of the inverter; and a current generator having a second transconductance amplifier configured to generate a reference current at an output of the current generator based on a reference voltage, the output of the current generator being coupled to the input of the inverter, where the output of the inverter is configured to be in a first state when a load current flowing through the sense resistive element is higher than a predetermined threshold, and in a second state when the load current is lower than the predetermined threshold, and where the predetermined threshold is based on the reference current.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

An amplifier includes a first input circuit, a second input circuit, a first compensation circuit, a second compensation circuit. The first input circuit changes a voltage level of the negative output node based on a first input signal. The second input circuit changes a voltage level of the positive output node based on a second input signal. The first compensation circuit changes the voltage level of the positive output node based on the first input signal. The second compensation circuit changes the voltage level of the negative output node based on the second output signal.

Circuits and methods for achieving good AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance in an amplifier. Embodiments provide an equalization approach which compensates for AM-AM and AM-PM variations in an amplifier by controlling bias voltage versus output power to alter the AM-AM and AM-PM profiles imposed by the amplifier. Differential amplifier embodiments include cross-coupled common-gate transistors that generate an equalization voltage that alters the gate bias voltage of respective main FETs in proportion to a power level present at the respective drains of the main FETs. Single-ended amplifier embodiments include an equalization circuit that alters the bias voltage to the gate of a main FET in proportion to a power level present at the main FET drain. Embodiments may also include a linearization circuit which alters the AM-PM profile of an input signal to compensate for the AM-PM profile imposed by a coupled amplifier.

A transimpedance amplifier (TIA) device design is disclosed. Symmetric components include first and second resistors R.sub.i, R.sub.fb, R.sub.e, R.sub.m, R.sub.x, R.sub.c, and R.sub.l, and transistors Q1-Q4. An optional mixer or cascode adds transistors Q5-Q8. Values for resistor components R.sub.x provide extended feedback gain tuning in a TIA-based current amplifier or mixer implementations without greatly affecting the input impedance or requiring more attenuators. Example values for resistor components R.sub.x range from about 50 to about 350 ohms.

Methods, systems, and devices for feedback for multi-level signaling in a memory device are described. A receiver may use a modulation scheme to communicate information with a host device. The receiver may include a first circuit, a second circuit, a third circuit, and a fourth circuit. Each of the first circuit, the second circuit, the third circuit, and the fourth circuit may determine, for a respective clock phase, a voltage level of a signal modulated using the modulation scheme. The receiver may include a first feedback circuit, a second feedback circuit, a third feedback circuit, and a fourth feedback circuit. The first feedback circuit that may use information received from the first circuit at the first clock phase and modify the signal input into the second circuit for the second clock phase.

A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a read element configured to generate a read signal when reading data from the magnetic media. A common-source common-gate (CS-CG) differential amplifier is coupled to the read element through a transmission line having a transmission line impedance Z.sub.0. A feedback circuit is coupled between an output of the CS-CG differential amplifier and an input of the CS-CG differential amplifier, wherein the feedback circuit is configured so that an input impedance of the CS-CG differential amplifier substantially matches the transmission line impedance Z.sub.0.

A low power comparator and a self-regulated device for adjusting power saving level of an electronic device are provided. The low power comparator includes an input differential pair circuit, a self-regulated device, and a tail current switch. The input differential pair circuit is configured to receive input signals to be compared. The self-regulated device is coupled to the input differential pair circuit and includes a self-regulated circuit which has a first transistor with a first threshold voltage and a second transistor with a second threshold voltage and is configured to adjust a power saving level of the low-power comparator according to the first threshold voltage and the second threshold voltage. The tail current switch is coupled to the input differential pair circuit through the self-regulated circuit to provide a constant current to the input differential pair circuit.

Disclosed is an operational amplifier based on a metal-oxide TFT. The operational amplifier includes an auxiliary amplifier and a bootstrap gain-increasing amplifier. The auxiliary amplifier adopts a two-stage positive feedback structure, including a fifth transistor, a seventh transistor, an eleventh transistor, a first amplifying unit, and a second amplifying unit. A gate of the fifth transistor serves as an input end of the operational amplifier. The bootstrap gain-increasing amplifier includes two second circuits in mutual symmetry. Each of the second circuits includes a first transistor, a second transistor, and a current source unit with a bootstrap structure.