Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-g.sub.m biasing to provide substantial immunity to process, temperature and voltage variations, for example. Various implementations of series peaking circuit-branch pre-emphasis may advantageously extend overall bandwidth of various circuits (e.g., high-speed track-and-hold circuits).

The present invention provides a circuit having a filter with an amplifier circuit for filtering and amplifying an input signal to generate an output signal, wherein a corner frequency of the filter is adjustable to control a settling time of the output signal.

A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.

There are disclosed various methods and apparatuses for amplifying a signal. In some embodiments of the method a signal is provided to an input (S) of a transconducting element (T) of an amplifier. An amplified signal is formed on the basis of the input signal by the transconducting element (T). The amplified signal is provided to an output stage. A negative conductance (R.sub.neg) in the output stage is used to adjust a gain and a noise figure of the amplifier. The amplified signal is provided via a feedback element (C.sub.fb) to another input (G) of the transconducting element (T). In some embodiments the apparatus comprises means for implementing the method.

A power amplification circuit includes a first transistor, which includes a source coupled to a first power supply and receives an input signal at a gate of the first transistor, a capacitor, which includes a first terminal and a second terminal, the first terminal being coupled to a drain of the first transistor, and a transformer, which is coupled between the second terminal and the gate of the first transistor, transforms a first signal input from the second terminal, and outputs a second signal having a phase different from a phase of the first signal to the gate of the first transistor. The first transistor outputs an output signal from the drain of the first transistor.

An amplifier including a first cascode circuit including a first transistor and a second transistor whose source or emitter is coupled to a drain or a collector of the first transistor, a second cascode circuit being a differential pair with the first cascode circuit, the second cascode circuit including a third transistor whose source or emitter is coupled to a source or an emitter of the first transistor and a fourth transistor whose source or emitter is coupled to a drain or collector of the third transistor, a first feedback path that couples between an output terminal of the third transistor and an input terminal of the first transistor, the first feedback path including a first capacitative element, and a second feedback path that couples between an output terminal of the first transistor and an input terminal of the third transistor, the second feedback path including a second capacitative element.

An operational amplifier based circuit has an operational amplifier, a feedback circuit, and a compensation circuit block. The feedback circuit is coupled between an output port and an input port of the operational amplifier. The compensation circuit block has circuits involved in stability compensation of the operational amplifier, wherein there is no stability compensation circuit driven at the output port of the operational amplifier.

An amplifying circuit includes a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage. The common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage. The common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.