An operational amplifier circuit in a display apparatus which is fast-acting to prevent voltage overshoot comprises a pre-operational amplifier module, an output operational amplifier module, and an output module. Driving current from the pre-operational amplifier module is the basis of the output operational amplifier module generating a dynamic bias voltage to the output module. The output operational amplifier module detects the dynamic bias voltage and adjusts the bias voltage to be level with a specified voltage based on at least one control voltage. When the dynamic bias voltage is less than the specified voltage, the output operational amplifier module pulls up the bias voltage and when the bias voltage is larger than the specified voltage, the output operational amplifier module pulls down the bias voltage. The pull up and pull down speeds are proportional to the at least one control voltage.

A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.

Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.

According to one embodiment, an operational amplifier includes first and second input terminals, an output terminal, differential circuitry, and output circuitry. The differential circuitry including first and second nodes, and first and second transistors. The output circuitry including third through fifth nodes, and third through eighth transistors. The third transistor being coupled to the first node at a gate and coupled to the third node at one end. The fourth transistor being coupled to the second node at a gate and coupled to the fourth node at one end. The fifth transistor being coupled to the fourth node at a gate and coupled to the third node at one end. The sixth transistor being coupled to the fourth node at each of a gate and one end.

Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.

A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.

An amplifier includes a first input transistor, a second input transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal. The first current mirror circuit is coupled to the first input transistor and the second input transistor. The second current mirror circuit is coupled to the first input transistor, the second input transistor, and the first current mirror circuit.

A half-power buffer amplifier includes an amplification unit including first and second nodes, the amplification unit configured to differentially amplify a differential input signal and to output a differentially amplified output signal, a first output unit including a first buffer unit between a first power source having a first voltage and a second power source having a second voltage, a second buffer unit between the first and second power sources, and a first switch unit between the first and second buffer units, and a second output unit including a third buffer unit between the second power source and a third power source having a third voltage, a fourth buffer unit between the second and third power sources, and a second switch unit between the third and fourth buffer units. Each of the first to third buffer units receives the differentially amplified output signal. The first switch unit is turned on or off based on or in response to a pre-driving control signal.

The present disclosure provides for transimpedance amplifiers for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines. The crossbar circuit may further include a transimpedance amplifier to generate an output voltage representative of a sum of currents flowing through a first bit line of the plurality of bit line. The transimpedance amplifier may include an operational amplifier, a current mirror circuit connected to an output of the operational amplifier, and one or more resistors connected to the current mirror circuit and a supply voltage.

A semiconductor circuit device includes a differential amplifier circuit and a switching signal output circuit. The differential amplifier circuit outputs a current based on an output voltage of a switching regulator. The switching signal output circuit outputs a switching signal for a switching device based on a voltage at an output node of the differential amplifier circuit and a voltage corresponding to an inductor current flowing through an inductor. The differential amplifier circuit includes a first output-stage transistor and a second output-stage transistor. The first output-stage transistor is provided between a first power supply node and a first node and outputs the current. The second output-stage transistor is provided between the first node and the output node and has a gate to which a first bias voltage is input.