Patent classifications
H
H03
H03F
2203/00
H03F2203/45
H03F2203/45366
H03F2203/45366
RECEIVER CIRCUIT FOR DOUBLE DATA RATE MEMORY, AND THE DOUBLE DATA RATE MEMORY USING THE RECEIVER CIRCUIT
A receiver circuit for double data rate memory is shown, which is operative to receive an input signal. The receiver circuit has two separated input circuits and a load-stage circuit. The first input circuit and the second input circuit in the input stage handle signals of non-overlapping signal swings. The input signal is received by an enabled input circuit of the first and the second input circuits. The load-stage circuit is coupled to the enabled input circuit to form a hybrid cascode circuit of a common-source and common-gate design.