A variable gain amplifier capable of stabilizing an average output potential of a differential output signal, improving power efficiency over a wide range of an amplitude of the differential input signal, and suppressing deterioration of a distortion rate is provided. The variable gain amplifier includes an amplifying circuit configured to amplify a differential input signal with a gain according to a gain control signal, and a current control circuit. The amplifying circuit has a first current source supplying a source current. The current control circuit adjusts a magnitude of the source current of the first current source according to a magnitude of the gain control signal.

A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.

A voltage-to-current converter includes a first differential pair of transistors, a second differential pair of transistors, and a first resistor. The first differential pair of transistors includes a first transistor and a second transistor. An emitter of the first transistor is directly connected to an emitter of the second transistor. The second differential pair of transistors includes a third transistor and a fourth transistor. An emitter of the third transistor is directly connected to an emitter of the fourth transistor. The first resistor is connected to the emitter of the first transistor, the emitter of the second transistor, the emitter of the third transistor, and the emitter of the fourth transistor.

The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a differential amplifier in cascode configuration. An input transistor is coupled to an output transistor via a peaking inductor. The output transistor is also directly coupled to a degeneration resistor. There are other embodiments as well.

A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.

A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.

An amplifier having improved linearity is disclosed. The amplifier includes a main transistor having a first current input terminal, a first current output terminal, and a first control terminal coupled to an RF input terminal that receives a signal voltage. A cascode transistor has a second current input terminal coupled to an RF output terminal for outputting an amplified signal. The cascode transistor has a second control terminal, and a second current output terminal coupled to the first current input terminal. Linearization circuitry has a bias output terminal coupled to the second control terminal. The linearization circuitry is configured to generate a bias signal at the bias output terminal to maintain a quiescent point of the main transistor for a given load coupled to the RF output terminal such that output conductance of the main transistor decreases nonlinearly with increasing main voltage and increases nonlinearly with decreasing main voltage.

A voltage-current converter includes a first input stage and a second input stage with a first transistor and a second transistor driven by the first input stage and by the second input stage, respectively. First and second current generators are coupled to current lines of the first transistor and of the second transistor. At least one resistor couples the current lines of the first transistor and of the second transistor, where the ends of the aforesaid resistor are coupled to feedback terminals of the input stages so that an input voltage applied between voltage input terminals of the input stages is converted into a current on respective current output terminals of the converter. The converter includes switching circuits for coupling the first and second current generators alternately to the current line of the first transistor and to the current line of the second transistor.

An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a single-to-differential variable gain amplifier having a variable resistor switch that substantially always operates in a triode region at all time. Said another way, the resistor switch is configured to operate in a triode region regardless of whether or not a first portion of an input signal to the variable gain amplifier is larger than a second portion of the input signal. The disclosed scheme helps to keep the variable resistor switch in the triode region in all cases of operation, thereby maintaining the linearity condition and reducing distortion in the variable gain amplifier.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.