A voltage-to-current converter circuit comprises an amplifier, a resistor, first and second feedback circuits, and an output circuit. The amplifier is configured to receive a differential input voltage signal. The resistor is coupled between first and second nodes of the amplifier. The first feedback circuit is coupled to a third node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a first range, and is turned off otherwise. The second feedback circuit is coupled to a fourth node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a second range different from the first range, and is turned off otherwise. The output circuit produces a differential current output signal having a value according to the value of the input voltage signal.

A circuit includes an operational amplifier, a plurality of input capacitors, a plurality of output capacitors, a plurality of sampling switches, a plurality of holding switches, a plurality of combined switches. The input capacitors include a first input capacitor and a second input capacitor. The output capacitors include a first output capacitor and a second output capacitor. The sampling switches include a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch. The holding switches include a first holding switch and a second holding switch. The combined switches include a first combined switch and a second combined switch.

This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has advantages of simple structure and low power consumption. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes: a first start-up transistor M16 and a second start-up transistor M17, a source of the first start-up transistor M16 and a source of the second start-up transistor M17 are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor M16 and a gate of the second start-up transistor M17 are configured to connect to a first bias voltage V.sub.b, and a drain of the first start-up transistor M16 and a drain of the second start-up transistor M17 are connected to input terminals of a second-stage or higher-stage amplifier.

This application provides an operational amplifier that increases the stability and settling speed of a common-mode feedback circuit. The operational amplifier includes N stages of amplifiers connected in series and M common-mode feedback circuits, where N and M are integers, N≥3, and N≥M>1. An i.sup.th common-mode feedback circuit in the M common-mode feedback circuits is configured to: detect a common-mode output voltage of a (j+b).sup.th stage of amplifier, and regulate an electrical parameter of at least one of the j.sup.th stage of amplifier to the (j+b).sup.th stage of amplifier, to stabilize the common-mode output voltage of the (j+b).sup.th stage of amplifier. An M.sup.th common-mode feedback circuit is configured to detect and stabilize a common-mode output voltage of an N.sup.th stage of amplifier. Herein i, j, and b are integers, M≥i≥1, N≥j≥1, i≥j, j+b≤N, and b≥0.

A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level.

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.

A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level.

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.

In one general aspect, an amplifier can include an input amplifier circuit configured to receive a bias current and receive, as an input, a signal pair connected differentially to the input amplifier circuit, the input amplifier circuit configured to output a differential output signal pair based on the received differential input signal pair, a feedback amplifier circuit configured to receive an average of the differential output signal pair and configured to provide a bias setting output for controlling the bias current, and an output buffer circuit configured to buffer the differential output signal pair, the buffering resulting in a buffered differential output signal pair capable of driving a resistive load.