The present invention is directed to electrical circuits. More specifically, embodiments of the presentation provide a CTLE module that includes a two compensation sections. A high-frequency zero RC section is in the source of the differential pair and close to the bias current source. A low-frequency zero section is coupled to an output terminal and configured outside the input signal path. A DC gain tuning section is coupled to the low-frequency zero section. There are other embodiments as well.

A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.

A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a 3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption.

A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

A capacitive gain amplifier circuit amplifies an input signal by a pair of differential amplifier circuits couples in series. The first differential amplifier circuit is reset during an autozero phase while disconnected from the second differential amplifier circuit, and the first and second differential amplifier circuits are connected together in series during a chop phase. A set of feedback capacitors is selectively switched in between respective outputs of the second differential amplifier circuit and respective inputs of the first differential amplifier circuit during the chop phase.

A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.

In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.

In high speed communication applications, e.g., optical communication, a variable gain amplifier is used for input signal amplitude normalization or for linear equalization. Traditionally a bipolar Gilbert multiplier circuit is used. When moving towards a low-power application, a modified circuit topology is implemented to reduce the minimum supply voltage requirement of the variable gain amplifier while ensuring that bias current levels remain substantially the same and achieving the same current switching capacity as the traditional circuit. As a result, the power consumption of the circuit can be greatly reduced. The modified circuit topology combines the amplifier and gain transistors and achieves gain programming using a voltage difference of two pairs of floating voltage sources.