An amplifier circuit for a millimeter wave (mmW) communication system includes an amplifier coupled to a matching network, and a variable gain control circuit in the matching network, the variable gain control circuit having an adjustable gain control resistance, the adjustable gain control resistance having adjustable segments and a center node therebetween, the center node coupled to an alternating current (AC) ground.

A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A power detector circuit that rejects the common mode portion of a differential signal is disclosed. The circuit includes a differential input having first and second input nodes. Differential and common mode circuit paths are coupled to the differential input. The common mode circuit path includes first and second capacitors coupled to respective first terminals of first and second input nodes of the differential input. The second terminal of each of the first and second capacitors is coupled to a gate terminal of a first bias transistor. The common mode circuit path is configured to reject a common mode portion of a differential input signal provided to the differential input such that a differential output signal is indicative of an amount of power of a differential portion of the differential input signal.

A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include a phase distortion compensation circuit. The phase distortion compensation circuit may include one or more n-type metal-oxide-semiconductor capacitors configured to receive a bias voltage. The bias voltage may be set to provide the proper amount of phase distortion compensation.

A power detector with wide dynamic range. The power detector includes a linear detector, followed by a voltage-to-current-to-voltage converter, which is then followed by an amplification stage. The current-to-voltage conversion in the converter is performed logarithmically. The power detector generates a desired linear-in-dB response at the output. In this power detector, the distribution of gain along the signal path is optimized in order to preserve linearity, and to minimize the impact of offset voltage inherently present in electronic blocks, which would corrupt the output voltage. Further, the topologies in the sub-blocks are designed to provide wide dynamic range, and to mitigate error sources. Moreover, the temperature sensitivity is designed out by either minimizing temperature variation of an individual block such as the v-i-v detector, or using two sub-blocks in tandem to provide overall temperature compensation. In one aspect, active resistors are used in order to compensate for temperature variations.

A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

An amplifier device and a duplexer circuit are provided. The amplifier device includes a first differential amplifier circuit and a controller. The first differential amplifier circuit includes first and second radio frequency (RF) input terminals, first and second transistors, first and second adjustable capacitor circuits, and first and second RF output terminals. The controller adjusts capacitance values of the first adjustable capacitor circuit of the first differential amplifier circuit and the second adjustable capacitor circuit of the first differential amplifier circuit according to at least one of a characteristic related to a first RF input signal of the first differential amplifier circuit, a characteristic related to the second RF input signal of the first differential amplifier circuit, a matching deviation between the first transistor and the second transistor of the first differential amplifier circuit, and a characteristic of the amplifier device.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.