A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.

An apparatus and method are provided for controlling the gain of a common source differential amplifier. The common source differential amplifier includes a pair of a metal-oxide-semiconductor field effect transistors (MOSFETs) each including a gate, a drain, and a source and at least one common source degeneration MOSFET in electrical communication between the sources of the pair of MOSFETs, the at least one common source degeneration MOSFET including a plurality of gate structures. A controller is in electrical communication with the gate structures and is configured to selectively activate one or more of the gate structures for controlling the gain of the common source differential amplifier.

An apparatus and method are provided for controlling the gain of a common source differential amplifier. The common source differential amplifier includes a pair of a metal-oxide-semiconductor field effect transistors (MOSFETs) each including a gate, a drain, and a source and at least one common source degeneration MOSFET in electrical communication between the sources of the pair of MOSFETs, the at least one common source degeneration MOSFET including a plurality of gate structures. A controller is in electrical communication with the gate structures and is configured to selectively activate one or more of the gate structures for controlling the gain of the common source differential amplifier.

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a variable gain amplifier (VGA) device that includes a low-gain tuning section and a high-gain tuning section. The low-gain tuning section includes both resistor and transistor elements. The high-gain tuning section includes a transistor element and is activated when an output gain is greater than a predetermined threshold level. There are other embodiments as well.

A circuit for spatial equalization, comprising: circuit elements each comprising four variable transconductors, in each of the circuit elements: an input of a first variable transconductor (VT) is connected to an input I and an output of the first VT is connected to an output I; an input of the second VT is connected to an input Q and an output of the second VT is connected to output I; an input of the third VT is connected to input I and an output of the third VT is connected to the output Q; and an input of the fourth VT is connected to input Q and an output of the fourth VT is connected to output Q; the input I of each of the first plurality of circuit elements are connected together; and the input Q of each of the first plurality of circuit elements are connected together.

The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.

A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.