A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.

An interface for inter-chip communication, comprises a transmitter part (TX) for transmitting a differential signal and a receiver part (RX) for receiving the differential signal, the transmitter part (TX) being provided in a first integrated circuit chip (CHIP A) and the receiver part (RX) being provided in a second integrated circuit chip (CHIP B). The transmitter part (TX) comprises a first transistor (Tx1) and a second transistor (Tx2) arranged in a common source configuration, and the receiver part (RX) comprises a third transistor (TR1) and a fourth transistor (TR2) arranged in a common gate configuration. Current flowing in the receiver part (RX) also flows through the transmitter part (TX).

Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

An interface for inter-chip communication, comprises a transmitter part (TX) for transmitting a differential signal and a receiver part (RX) for receiving the differential signal, the transmitter part (TX) being provided in a first integrated circuit chip (CHIP A) and the receiver part (RX) being provided in a second integrated circuit chip (CHIP B). The transmitter part (TX) comprises a first transistor (Tx1) and a second transistor (Tx2) arranged in a common source configuration, and the receiver part (RX) comprises a third transistor (TR1) and a fourth transistor (TR2) arranged in a common gate configuration. Current flowing in the receiver part (RX) also flows through the transmitter part (TX).

A fully balanced differential difference amplifier includes a first differential input stage that receives an input voltage and a second differential input stage that receives a common-mode voltage. A first resistive-degeneration group is coupled to the first differential input and a second resistive-degeneration group is coupled to the second differential input. A differential output stage generates an output voltage. A first switch is coupled in parallel to the first resistive-degeneration group and a second switch is coupled in parallel with the second resistive-degeneration group. The first and second switches are driven into the closed state when the voltage input assumes a first value such that said first input stage operates in the linear region, and are driven into the open state when the voltage input assumes a second value, higher than the first value, such that the first input stage operates in a non-linear region.

Provided herein are apparatus and methods for a multi-stage signal-processing circuit. The signal-processing circuit can include multiple configurable stages that can be cascaded and configured to process an input signal. Control circuitry can be used to select an output of the configurable stages. Serial data can be recovered with good signal integrity using a signal monitor with the configurable stages by virtually placing the signal monitor on a buffered output node.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Methods and systems for receiving a differential input voltage signal at an input of a variable gain amplifier, and responsively generating an amplified differential output voltage signal on a pair of output nodes by driving a pair of load impedances connected to the pair of output nodes with an amplifier current according to the differential input voltage signal, enabling a cross-coupled differential pair connected in parallel to the pair of load impedances, the cross-coupled differential pair having drain inputs and cross-coupled gate inputs connected to the pair of output nodes to supplement a gain of the amplified differential voltage output voltage signal, and reducing a common mode voltage of the amplified differential output voltage signal by lowering the amplifier current driving the pair of load impedances via a bias control signal, the amplifier current lowered responsive to detecting the supplemented gain of the amplified differential output voltage signal.

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

Low power radio frequency (RF) receivers and related circuits are described.