A processing device for position sensing includes a plurality of light sensors, a signal processing unit, a current mirror unit and a transforming unit. The light sensors are spaced apart from each other and sense a light field to generate a plurality of position sensing current signals. The signal processing unit receives the position sensing current signals and provides a load isolation, so as to generate a first current signal and a second current signal. The second current signal is transmitted to a node. The first and second current signals respectively correspond to a first group and a second group of light sensors. The current mirror unit mirrors the first current signal to a third current signal. The third current is transmitted to the node. The transforming unit transforms a differential current signal formed by the second and third current signals on the node to a voltage signal.

Techniques for shielding wearable surface electromyography (sEMG) devices are described. According to some aspects, an sEMG device may comprise amplification circuitry comprising at least a first differential amplifier and at least two sEMG electrodes electrically connected to the amplification circuitry. The device may further comprise at least one auxiliary conductor not electrically connected to the amplification circuitry, wherein the at least one auxiliary conductor is configured to be electrically coupled to a wearer of the wearable device, and an electromagnetic shield surrounding the wearable device at least in part and electrically connected to the at least one auxiliary conductor.

Frequency selective analog front-end circuitry, used to convert a sensed charge signal to an analog voltage is disclosed. In one aspect, the frequency selective analog front-end circuitry includes an op-amp having an output, an inverting input and a noninverting input, a first resistor connected between the terminal of the first capacitor and the inverting input of the op-amp, a second capacitor connected between the output of the op-amp and the inverting input of the op-amp, a second resistor connected between the output of the op-amp and the inverting input of the op-amp, a third capacitor connected between the terminal of the first capacitor and the noninverting input of the op-amp, and a third resistor connected between the noninverting input of the op-amp and a reference voltage.

A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.

The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.

A preamplifier comprises an input stage and a capacitive coupling stage. The input stage is arranged to receive a differential signal from a magnetic resistor which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state. The capacitive coupling stage has an input arranged to receive the differential signal from the input stage, a filter comprising a first resistor, a second resistor, a first capacitor, a second capacitor, and switches arranged in parallel with respective resistors, where the switches are closed when the preamplifier is powered on from the off state to an on state. A switch control is arranged to determine that an offset of the differential signal has settled and open the switches based on the determination.

Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

A tunable filter is described where the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end tuning applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. The tunable filter topology is applicable for both transmit and receive circuits. A method is described where the filter characteristics are adjusted to account for and compensate for the frequency response of the antenna used in a communication system.

A low power radio frequency (RF) signal detector comprising a set of transistors, a bias input circuitry configured to apply bias to each of the set of transistors, and a differential signal input circuitry configured to apply a pair of differential signals to the set of transistors, wherein the pair of differential signals increases or decreases bias applied to the set of transistors to achieve low power, high frequency RF signal detection.

A low power radio frequency (RF) signal detector comprising a set of transistors, a bias input circuitry configured to apply bias to each of the set of transistors, and a differential signal input circuitry configured to apply a pair of differential signals to the set of transistors, wherein the pair of differential signals increases or decreases bias applied to the set of transistors to achieve low power, high frequency RF signal detection.