A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

An analog to digital converter (ADC) includes a conversion circuit digitizing an input analog signal to produce an output digital signal. A current generator generates a constant bias current. A current mirror circuit includes an input transistor receiving the constant bias current, an output transistor in a mirroring relationship with the input transistor and generating a variable bias current, and a parallel transistor circuit selectively coupling a parallel transistor in parallel with the input transistor or the output transistor in response to a control signal. The control signal is representative of the conversion rate of the ADC. A buffer generates a common mode voltage for use by the conversion circuit, from the variable bias current.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

An amplifier includes: a signal polarity inversion circuit which modulates an input signal and outputs a modulation signal; an amplifier circuit which is constituted from an operational transconductance amplifier (OTA) to amplify the modulation signal and output a current; and a sample-hold circuit having a sampling capacitor which is charged and discharged by selective sampling of the output current of the amplifier circuit and a holding capacitor to which the voltage of the sampling capacitor is transferred.

Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.

A signal processing circuit, which has a pair of input nodes and a pair of output nodes, includes a first switch pair, a second switch pair, an amplifier, a first compensation capacitor and a second compensation capacitor. The first switch pair is coupled between the pair of input nodes and a plurality of floating nodes. The second switch pair is coupled between the plurality of floating nodes and the pair of output nodes. The amplifier is coupled between the plurality of floating nodes and the pair of output nodes. The first compensation capacitor is coupled between a first floating node among the plurality of floating nodes and a first output node among the pair of output nodes. The second compensation capacitor is coupled between a second floating node among the plurality of floating nodes and the first output node.

A system has an output and receives an input signal. An operational amplifier has an input, an output and an offset at the input. A switched capacitor network samples the input signal at a switched capacitor frequency. An autozeroing capacitor connected to the input of the operational amplifier captures the offset during an offset capture interval according to an autozeroing frequency. Chopping and autozeroing switches, connected between the autozeroing capacitor and the switched capacitor network, chop the sampled input signal according to a chopping frequency and autozero the captured offset according to the autozeroing frequency. De-chopping switches, connected between the output of the operational amplifier and the output of the system, operate on the output of the operational amplifier at the chopping frequency to chop the autozeroed captured offset and de-chop the chopped sampled input signal processed by the operational amplifier.

Signal quality is improved in a circuit for amplifying and sampling an analog signal. An input signal is input to one end of an input-side resistor. An operational amplifier amplifies the input signal, and outputs the input signal from an output terminal as an amplified signal. One end of a filter capacitor is connected to an input terminal of the operational amplifier. A predetermined frequency component of the input signal passes through the filter capacitor. A sampling capacitor imports the amplified signal during a predetermined sampling period, and holds the amplified signal during a predetermined hold period. A sampling switch connects the output terminal of the operational amplifier to one end of the sampling capacitor during the sampling period, and disconnects the output terminal of the operational amplifier from one end of the sampling capacitor during the hold period. A cutoff circuit disconnects the input-side resistor from one end of the filter capacitor during the sampling period, and connects the input-side resistor to one end of the filter capacitor during the hold period.

A data storage apparatus includes storage, and a controller including an internal voltage trimming circuit and controlling the storage in response to a request from a host. The trimming circuit may include an integral circuit sampling a difference between a test voltage output by a device under test and a reference voltage, generating an integral signal by integrating a sampled signal, and including an offset cancellation unit cancelling an offset from the sampled signal, a comparison circuit generating a comparison signal by comparing the integral signal with the reference voltage, a code generation circuit receiving an initial trimming code and generating preliminary trimming codes by increasing or decreasing the initial trimming code in response to the comparison signal, and a code average signal generation circuit generating the final trimming code is by averaging the preliminary trimming codes for a given time and provide the final trimming code to the storage.

A high voltage sensing circuit included in a display driver integrated circuit includes a plurality of channels, a plurality of sampling capacitors, an amplifier and a feedback capacitor. The plurality of channels receives a plurality of input voltages. The plurality of sampling capacitors are connected to the plurality of channels, respectively, to simultaneously sample the plurality of input voltages. The amplifier is configured to sequentially receive each of a plurality of sampled input voltages to sequentially generate a respective plurality of sensing voltages. The feedback capacitor is connected between an input terminal and an output terminal of the amplifier, and is shared by the plurality of channels. The amplifier and the feedback capacitor are configured such that each of the plurality of sampled input voltages is sequentially scaled to the respective one of the plurality of sensing voltages by the amplifier and the feedback capacitor.