A system has an output and receives an input signal. An operational amplifier has an input, an output and an offset at the input. A switched capacitor network samples the input signal at a switched capacitor frequency. An autozeroing capacitor connected to the input of the operational amplifier captures the offset during an offset capture interval according to an autozeroing frequency. Chopping and autozeroing switches, connected between the autozeroing capacitor and the switched capacitor network, chop the sampled input signal according to a chopping frequency and autozero the captured offset according to the autozeroing frequency. De-chopping switches, connected between the output of the operational amplifier and the output of the system, operate on the output of the operational amplifier at the chopping frequency to chop the autozeroed captured offset and de-chop the chopped sampled input signal processed by the operational amplifier.

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to calculate the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.

An Alternating Current (AC) and Direct Current (DC) coupled electronic receiver system including a receiver, an AC-coupling capacitor between an input of the receiver system and the receiver, a bypass switch configured to selectively bypass the AC-coupling capacitor to DC-couple the input to the receiver, a bypass switch driving circuit configured to cause the bypass switch to switch ON and thereby DC-couple the input to the receiver, and cause the bypass switch to switch OFF and thereby AC-couple the input to the receiver, and a voltage-following transistor between a source and a gate of the bypass switch configured to maintain an OFF state of the bypass switch while the input is AC-coupled.

A signal processing circuit that achieves functionality similar to that of a switched capacitor circuit without the necessity a clock. The circuit compensates for finite open loop gain and for offset voltages in the components, allowing the circuit to calculate the result of a problem represented by the circuit essentially immediately upon the presentation of a new input or set of inputs. After the circuit is initialized to remove gain, an input is applied to the circuit, and propagates through the network and affects the state of amplifier outputs; the propagation from the input through capacitors to the ultimate output(s) of the circuit is the analog calculation taking place. The calculation is not mediated by a clock, but rather the calculation corresponds to the circuit's one-time response to the application of the inputs. Using these techniques complex signal processing circuits and even analog neural networks may be constructed.

Apparatuses and techniques are described for calibrating a negative voltage source. A ground voltage is applied to a multi-stage amplifier from the negative voltage source while an offset voltage measurement (OVM) is made at the output of the multi-stage amplifier. The OVM is recorded and subsequently used by a calibration circuit when the negative voltage source applies a range of negative voltages to the input of the multiple stage amplifier. The calibration circuit subtracts the OVM from measurements obtained at the output of the multi-stage amplifier to obtain corrected measurements, and uses the corrected measurements to calibrate the negative voltage source, e.g., by adjusting a relationship between digital values input to the negative voltage source and the output voltages.

An apparatus may include a transistor, a capacitor, and an operational amplifier. The transistor may have a sub-threshold voltage applied to a gate of the transistor. The capacitor configured to store a first gate to-source voltage of the transistor while a first switch and a second switch are closed and a third switch is open. The capacitor may be charged to a first gate-to-source voltage of the transistor while the transistor is biased with a first bias current. The operational amplifier may be configured to determine a voltage difference between the first gate-to-source voltage stored in the capacitor and a second gate-to-source voltage of the transistor while the transistor is biased with a second bias current. The operational amplifier may determine the voltage difference while the third switch is closed and the first switch and the second switch are open. The voltage difference may correspond to a temperature of the transistor.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

An inverse pseudo fully-differential amplifier having a common-mode feedback control circuit and a method for maintaining a stable output common-mode level are provided. The inverse pseudo fully-differential amplifier includes the pseudo fully-differential operation circuit and a common-mode feedback control circuit. The pseudo fully-differential operation circuit includes inverter amplifiers (2) and (3). The inverter amplifiers (2) and (3) respectively have a first feedback control terminal and a second feedback control terminal. Input terminals of the common-mode feedback control circuit are respectively connected with output terminals of the inverter amplifier (2) and (3), and are configured to detect common-mode output voltages of the inverter amplifier (2) and (3). An output terminal of the common-mode feedback control circuit is connected with the first feedback control terminal and the second feedback control terminal, and is configured to generate common-mode feedback to the inverter amplifiers (2) and (3) to maintain a stable common mode output level.