Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

Briefly, embodiments of claimed subject matter relate to determination of a high-impedance state or a low-impedance state of a resistive memory element over a wide range of temperature, such as temperatures approaching 40.0 C. to temperatures approaching +125.0 C. Such determination may be brought about by implementing a circuit which, according to various embodiments described herein, emulates a reference impedance having a negative temperature coefficient.

There is provided a differential amplifier including: an inverting input terminal to which a first voltage is applied; a non-inverting input terminal to which a second voltage proportional to the first voltage is applied; and an offset part configured to generate a predetermined input offset voltage between the inverting input terminal and the non-inverting input terminal.

An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

In examples, an apparatus for sensing current comprises a power transistor; a sense transistor coupled to the power transistor; and an offset addition circuit coupled to the power transistor and the sense transistor, the offset addition circuit comprising a first pair of transistors and a differential amplifier. The apparatus also comprises a cascode amplifier circuit coupled to the offset addition circuit, the cascode amplifier circuit comprising a second pair of transistors, and a gain trim circuit coupled to the cascode amplifier circuit, the gain trim circuit including another differential amplifier and a third transistor. The apparatus further includes an analog-to-digital converter (ADC) coupled to the gain trim circuit and storage coupled to the ADC.

A circuit arrangement for generating a supply voltage with a controllable ground potential level includes a voltage source that provides the supply voltage ungrounded, a control unit that generates an adjustable control d.c. voltage to ground, and an operational amplifier that is connected via its voltage supply terminals to the supply voltage source, where the control d.c. voltage is applied to the inverting input of the operational amplifier, the non-inverting input of the operational amplifier is connected via a resistor network to the voltage source and to a ground terminal and the output of the operational amplifier is fed back to the inverting input via a capacitor.

A gain amplifier of a sensing circuit for sensing degradation of an OLED display panel, the gain amplifier comprising: an operation amplifier; and a plurality of gain amplifier cells sequentially coupled to the operation amplifier. Each of the gain amplifier cells comprises a plurality of capacitors each placed between two internal nodes of the gain amplifier cell, excluding a ground node, such that a voltage gain of the gain amplifier and a DC offset of the gain amplifier are determined according to capacitances of the capacitors without considering parasitic capacitance.

An operational amplifier circuit includes a potential control circuit connected between a current sense semiconductor element connected in parallel with a main semiconductor element and a current detection resistor. The potential control circuit controls an output potential of the current sense semiconductor element to be equal to that of the main semiconductor element. The potential control circuit includes a current control element controlling an output current of the current sense semiconductor element and an operational amplifier outputting a signal corresponding to an output potential difference between the current sense semiconductor element and the main semiconductor element to the current control element. An input offset voltage polarity determination unit determines a polarity of an input offset voltage of the operational amplifier according to the output potential difference. The polarity of the input offset voltage is controlled to be constant based on polarity determination of the input offset voltage.

A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.

In order to realize a circuit in a subsequent stage with a smaller circuit scale with respect to a single-ended input of a large signal, a double-sampling switched-capacitor input circuit includes a first switched-capacitor input circuit, which includes first capacitors for double sampling, and a second switched-capacitor input circuit, which includes second capacitors for double sampling, and which is configured to operate in opposite phase to the first switched-capacitor input circuit, the double-sampling switched-capacitor input circuit having a configuration in which the first capacitors and the second capacitors have different values, and in which the value of the second capacitors is adjusted so that a signal is attenuated.