An offset cancellation circuit and method are provided where successive stages of cascaded amplifiers are operated in a saturated state. Biasing is provided, by a feedback amplifier, connected in a feedback loop for each cascaded amplifier, so as to be responsive, in a non-saturated state, to the input of an associated amplifier stage operating in the saturated state.

An amplifier circuit can have a differential input. A common-mode signal present at the differential input can induce an offset voltage at an output of the amplifier circuit. A compensation can be performed to reduce or eliminate such an offset, such as at a first temperature. Circuits and techniques for drift correction can be performed, such as to correct for residual offset error across an entirety of a specified operation temperature range. In an example, first and second drift correction signal generator circuits can be used, such as to provide signals proportional to a common mode voltage, but having different temperature coefficients.

In accordance with embodiments of the present disclosure, a method for power supply rejection for an amplifier may include generating a correction signal by multiplying a quantity indicative of a power supply voltage of the amplifier by a transfer function defining a response from the power supply voltage of the amplifier to an output signal of the amplifier and subtracting the correction signal from a signal within a signal path of a circuit comprising the amplifier.

An amplifier circuit can have a differential input. A common-mode signal present at the differential input can induce an offset voltage at an output of the amplifier circuit. A compensation can be performed to reduce or eliminate such an offset, such as at a first temperature. Circuits and techniques for drift correction can be performed, such as to correct for residual offset error across an entirety of a specified operation temperature range. In an example, first and second drift correction signal generator circuits can be used, such as to provide signals proportional to a common mode voltage, but having different temperature coefficients.

In at least one embodiment, a fully differential amplifier is provided. A first amplifying circuit receives a first input voltage signal and provides a first output voltage signal. A second amplifying circuit to receive a second voltage signal and to provide a second output voltage signal. A summing circuit to provide a common mode component of the first input voltage signal and the second input voltage signal. A compensation circuit to amplify the common mode component of the first input voltage signal and the second input voltage signal and output an injection signal. A common gain setting network including a plurality of resistors to receive the injection signal and to interface with the first amplifying circuit, the second amplifying circuit, and the compensation circuit to prevent the common mode component from being present in the first output voltage signal and the second output voltage signal.

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.

An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

An apparatus includes a first amplifier, a second amplifier, and a compensation-setting generator to generate a first amplifier compensation setting and second amplifier compensation setting. A controller is operable to: i) apply the first amplifier compensation setting to the first amplifier and apply the second amplifier compensation setting to the second amplifier. The controller is further operable to switch between generating updates to the first amplifier compensation setting and the second amplifier compensation setting.

To provide a variable gain amplifier capable of correcting a DC offset voltage through simpler control even when a gain thereof is changed. A differential output type variable gain amplifier is equipped with a first voltage correction unit coupled to a preceding stage of a variable gain amplifier circuit and for outputting a first correction voltage to correct a potential difference generated between a first conductor provided with a first input resistor and a second conductor provided with a second input resistor, and a second voltage correction unit coupled to a subsequent stage of the variable gain amplifier circuit and for correcting a differential output. A control unit is configured to control the first correction voltage and a correction amount of a potential difference by the second voltage correction unit and thereby attenuate a DC offset voltage included in the differential output.

Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.