An audio amplifier of a BTL (Bridged Tied Load) type, includes a first amplifier, a second amplifier, a first output pin connected to an output of the first amplifier, a second output pin connected to an output of the second amplifier, a first monitor pin, a second monitor pin, a current source connected to the first monitor pin and configured to be switched on and off, a switch interposed between the second monitor pin and a fixed voltage line, and a load state determination circuit configured to detect a state of a load based on a potential difference between the first monitor pin and the second monitor pin.

A circuit device includes a differential circuit including differential input terminals; a differential amplifier circuit in which differential input nodes are connected to the differential input terminals; a first power supply terminal supplied with a first voltage; a second power supply terminal supplied with a second voltage; a common terminal; a first resistive element of which one end is connected to one differential input terminal and another end is connected to the common terminal; a second resistive element of which one end is connected to the first supply terminal and another end is connected to the common terminal; a third resistive element of which one end is connected to one differential input terminal and another end is connected to the second supply terminal; a bonding wire, and a capacitor of which one end is connected to the second supply terminal and another end is connected to the common terminal.

Distributed amplifier systems and methods are disclosed. An example distributed amplifier system includes first stage traveling wave amplifier (TWA) circuitry that is controllable to provide one of a first set of discrete gain settings. The first stage TWA circuitry includes a first input transmission line, a first output transmission line, and a first plurality of amplifiers coupled antiparallel between the first input transmission line and the first output transmission line. The first set of discrete gain settings has approximately constant logarithmic spacing.

In an exemplary embodiment, a plurality of differential amplification circuits has: first differential amplification circuits each including a differential pair circuit to generate the differential signal according to the differential input signal, a delay line, and a current source to supply a current to the differential pair circuit via the delay line; and second differential amplification circuits each including a differential pair circuit to generate the differential signal according to the differential input signal, and a current source to directly supply a current to the differential pair circuit. The first differential amplification circuits and the second differential amplification circuits are mutually connected in parallel between the pair of input-side transmission lines and the pair of output-side transmission lines.

A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.

An circuit device includes a differential circuit including differential input terminals; a differential amplifier circuit in which differential input nodes are connected to the differential input terminals; a first power supply terminal applied a first voltage to; a second power supply terminal applied a second voltage to; a common terminal; a first resistive element of which one end is connected to one differential input terminal and another end is connected to the common terminal; a second resistive element of which one end is connected to the first supply terminal and another end is connected to the common terminal; a third resistive element of which one end is connected to one differential input terminal and another end is connected to the second supply terminal; a bonding wire, and a capacitor of which one end is connected to the second supply terminal and another end is connected to the common terminal

A traveling wave amplifier includes two input-side lines, two output-side lines, and amplification cells, and the amplification cells include a first input terminal, a second input terminal, a transistor including a base connected to the first input terminal and a collector connected to one of the output-side lines, a transistor including a base connected to the second input terminal and a collector connected to the other output-side line, a current source connected to an emitter of the two transistors, a series circuit having one end connected to the collector of the other transistor and the other end connected to the base of the one transistor and including a capacitor and a resistor, and a series circuit having one end connected to the collector of the one transistor and the other end connected to the base of the other transistor and including a capacitor and a resistor.

In an exemplary embodiment, a plurality of differential amplification circuits has: first differential amplification circuits each including a differential pair circuit to generate the differential signal according to the differential input signal, a delay line, and a current source to supply a current to the differential pair circuit via the delay line; and second differential amplification circuits each including a differential pair circuit to generate the differential signal according to the differential input signal, and a current source to directly supply a current to the differential pair circuit. The first differential amplification circuits and the second differential amplification circuits are mutually connected in parallel between the pair of input-side transmission lines and the pair of output-side transmission lines.

A differential amplifier is disclosed. The differential amplifier includes: a pair of input terminals externally receiving an input signal; a first differential pair including a first transistor, a second transistor, a first resistor, and a second resistor and configured to generate a first signal; a second differential pair including a third transistor, a fourth transistor, a third resistor, and a fourth resistor and configured to generate a second signal; a current source connected to the first, second, third, and fourth resistors and configured to provide a current to the first and second differential pairs; a pair of level shifters configured to generate a shifted signal from the input signal; and a pair of output terminals externally outputting an output signal containing the first and second signals, wherein the first and second transistors receive the input signal and the third and fourth transistors receive the shifted signal.