An apparatus is disclosed for reducing resistor conductivity modulation during amplification. In an example aspect, the apparatus includes a power amplifier circuit comprising a first pair of resistors, a digital-to-analog converter comprising a second pair of resistors, a reference generation circuit comprising a third pair of resistors, and a scaling circuit. The scaling circuit is configured to accept a common-mode reference voltage and a common-mode output voltage. The scaling circuit is also configured to provide a first voltage at body terminals of the first pair of resistors, a second voltage at body terminals of the second pair of resistors, and a third voltage at body terminals of the third pair of resistors such that a summation of the first voltage and the third voltage reduced by the second voltage is approximately equal to an average of the common-mode reference voltage and the common-mode output voltage.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a common-mode reference voltage generation circuit uses one or more additional sampling switched capacitors to selectively couple the first and second reference voltages to the amplifier input during the gain phase when the input voltage is between the high and low threshold voltages using a switching configuration of switches that are controllable to connect the sampling switched capacitors to the one or more central nodes in the sampling phase, and to connect the amplifier output in feedback to the input sampling circuit in the gain phase while simultaneously connecting the one or more central nodes to the first amplifier input.

Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.

A method for matching a pair of composite circuit elements (CEs) included in a circuit includes fabricating N CEs (e.g., resistors, transistors, current sources, capacitors) designed to match and switches configurable, according to M different combinations, to connect N/2 of the N CEs to form a first composite CE and to connect a remaining N/2 of the N CEs to form a second composite CE. Sequentially in time, for each combination of the M combinations, the switches are configured to form the first and second composite CEs according to the combination and a characteristic of the circuit is measured that includes the formed first and second composite CEs. The characteristic indicates how well the formed composite CEs match. A final combination of the M combinations is chosen whose measured characteristic indicates a best match and the final combination is used to configure the switches to form the composite CEs.

A display device includes an output circuit including a differential amplifier circuit, an output amplifier circuit that includes a first transistor of the first conduction type coupled between the first supply terminal and the output terminal, and including a control terminal coupled to the differential amplifier circuit, a first control circuit, an input terminal, an output terminal, and first to third supply terminals to which first to third supply voltages are applied, wherein the third supply voltage is set to a voltage between the first supply voltage and the second supply voltage, or the second supply voltage, and wherein the first control circuit includes a third transistor and a first switch which are coupled in series between the first supply terminal and the control terminal of the first transistor.

Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.

Apparatus (301) for switchable attenuation of a differential input signal from a microphone includes positive and negative non-attenuating paths (406, 410) have n- and p-type MOSFETs (421, 422, 423, 424) in back-to-back configurations; positive and negative attenuating paths (405, 409) have n- and p-type MOSFETs (415, 416, 418, 419) in back-to-back configurations in combination with resistors; a gate driver (425) applies a drive signal of one polarity (QNEG) to gates of the n-type MOSFETs in the attenuating paths and the p-type MOSFETs in the non-attenuating paths, and a drive signal of opposite polarity (QPOS) to the gates of the p-type MOSFETs in the attenuating paths and the n-type MOSFETs in the non-attenuating paths; and the state of the MOSFETs depends on the drive signals at their gates, and thus the input signal may be routed via either the non-attenuating paths or the attenuating paths by controlling the drive signals.

Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.