A semiconductor device includes an output driving circuit configured to output an output current to an output terminal; a detection resistor connected between the output terminal and the output driving circuit; an amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor; a current generation circuit configured to output a reference current; a reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current; an A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference; and a control circuit configured to control the output current output from the output driving circuit according to the digital detection signal. The detection resistor has a same temperature characteristics as the reference resistor.

Provided are a semiconductor device and a sensor system capable of achieving improvement of noise resistance. Thus, an output circuit 106a in the semiconductor device includes: input terminals 207n, 207p; and an output terminal 208; an output amplifier 201 connecting the input terminals 207n, 207p to the output terminal 208; a feedback element 203 returning the output terminal 208 to the input terminal 207n; a switching transistor 204; and a resistance element 206. A drain of the switching transistor 204 is connected to the input terminal 207n. The resistance element 206 is provided between a back gate of the switching transistor 204 and a power source Vdd and has impedance of a predetermined value or more for suppressing noise of a predetermined frequency generated at the input terminal 207n.

A switched capacitor amplifier circuit includes an operational amplifier, a first capacitor and a second capacitor each having one end connected to a negative input terminal of the operational amplifier, a first switching circuit configured to connect the other end of the first capacitor and a signal source during a first operation, a second switching circuit configured to connect the other end of the second capacitor and the output terminal of the operational amplifier so as to connect the output terminal and the negative input terminal of the operational amplifier through the second capacitor during the second operation, and an impedance converter circuit configured to convert an output impedance of the signal source into a specified impedance, the impedance converter circuit being connected between the first switching circuit and the other end of the first capacitor.

A current sensing circuit includes load transistors having a current path coupled between a power terminal and corresponding load terminals, sense transistors having a current path coupled between the power terminal and corresponding sense terminals, each sense transistor being coupled to a respective load transistor, N-channel transistors having a current path coupled between a respective sense transistor and a respective sense terminal, an amplifier for selectively equalizing the voltages across one of the load transistors and one of the sense transistors, and bypass circuits coupled to a bulk terminal of the N-channel transistors.

A receiver includes a first T-coil circuit at an input of the receiver and configured to receive an input signal, a termination impedance coupled to the first T-coil circuit and configured to match an impedance of a transmission line coupled to the first T-coil circuit, and an amplifier including a first input and a second input and configured to amplify a differential signal at the first and second inputs, a calibration switch coupled to the amplifier and configured to selectively electrically connect or disconnect the first and second inputs of the amplifier, and a first receive switch configured to selectively electrically connect or disconnect a center node of the first T-coil circuit and the amplifier.

A data storage apparatus includes storage and a controller configured to control the storage in response to a request from a host. The controller includes an internal voltage trimming circuit which includes: an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage; a transition detection circuit configured to output a detection signal according to level transition of the comparison signal; a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the storage.

A readout circuit for reading sensed signals of a pixel array. The readout circuit includes: an operational amplifier, a plurality of switching devices and a computation circuit. The operational amplifier is arranged to generate an output signal in each amplifier output cycle. In each amplifier output cycle, each of the switching devices is controlled by a switch controlling signal to selectively couple pixel circuits to the differential input terminals of the operational amplifier. The computation circuit is arranged to the recover a plurality of sensed signal respectively corresponding to a plurality of pixel circuits. In each amplifier output cycle, at least two of the switching devices are turned on, such that the operational amplifier receives the sensed signals of at least two pixel circuits in the pixel array simultaneously and sums the sensed signals of the at least two pixel circuits to generate the output signal.

A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.

Technologies relating to RRAM-based crossbar array circuits and more specifically to reducing row switch resistance error of in crossbar array circuits are disclosed. An example apparatus includes: a first Op-amp including a first inverting Op-amp input, a first non-inverting Op-amp input, and a first Op-amp output; a row switch device including a row switch input and a row switch output; a crossbar array including a row wire, a column wire, and a cross-point device connected between the row wire and the column wire. The row switch input is connected to the first Op-amp output; the row switch output is connected to the first inverting Op-amp input; and the row switch output is connected to the row wire.

A reference buffer circuit comprises a dual-difference amplifier circuit including a first differential input, a second differential input, and a differential output that provides a differential reference signal; a first reference voltage coupled to a first input of the first differential input and a second reference voltage coupled to a first input of the second differential input; and wherein outputs of the differential output are connected by a feedback circuit path to second inputs of the first and second differential inputs.