Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

An audio amplifier of a BTL (Bridged Tied Load) type, includes a first amplifier, a second amplifier, a first output pin connected to an output of the first amplifier, a second output pin connected to an output of the second amplifier, a first monitor pin, a second monitor pin, a current source connected to the first monitor pin and configured to be switched on and off, a switch interposed between the second monitor pin and a fixed voltage line, and a load state determination circuit configured to detect a state of a load based on a potential difference between the first monitor pin and the second monitor pin.

The present application provides a window function processing module including an integrating circuit, configured to receive an integrating input signal, the integrating circuit comprising an operational amplifier; an integrating capacitor, coupled to an output terminal and a first input terminal of the operational amplifier; and an adjustable impedance module, coupled between the first input terminal of the operational amplifier and an integrating input terminal of the integrating circuit, wherein the adjustable impedance module is controlled by at least one control signal to adjust an impedance value of the adjustable impedance module; and a control unit, coupled to the integrating circuit, configured to generate the at least one control signal according to a window function, to adjust the integration gain of the integrating circuit, such that the integrating output signal is related to an operation result of the integrating input signal and the window function.

A switch for controlling a gain of an amplifier comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a first resistor, and an inverter. A source of the first NMOS transistor is connected to a first terminal of the first resistor, a drain of the first NMOS transistor is connected to a drain of the third PMOS transistor, a source of the fourth NMOS transistor and a source of the second NMOS transistor, a gate of the first NMOS transistor is connected to a source of the third PMOS transistor, a drain of the fifth PMOS transistor, a drain of the fourth NMOS transistor, and a gate of the second NMOS transistor; a gate of the third PMOS transistor receives a switch voltage (Vs); a gate of the fourth PMOS transistor receives a negative switch voltage (Vsn).

A switch for controlling a gain of an amplifier comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a first resistor, and an inverter. A source of the first NMOS transistor is connected to a first terminal of the first resistor, a drain of the first NMOS transistor is connected to a drain of the third PMOS transistor, a source of the fourth NMOS transistor and a source of the second NMOS transistor, a gate of the first NMOS transistor is connected to a source of the third PMOS transistor, a drain of the fifth PMOS transistor, a drain of the fourth NMOS transistor, and a gate of the second NMOS transistor; a gate of the third PMOS transistor receives a switch voltage (Vs); a gate of the fourth PMOS transistor receives a negative switch voltage (Vsn).

The present invention provides a circuit having a filter with an amplifier circuit for filtering and amplifying an input signal to generate an output signal, wherein a corner frequency of the filter is adjustable to control a settling time of the output signal.

An amplifier circuit can include an amplifier and a resistor network coupled to the amplifier. The resistor network can include a range resistor coupled in parallel to a resistor string, and one or more switches coupled to the resistor string. The resistor network can be used to calibrate gain and common mode rejection ratio (CMRR) of the amplifier circuit.

A semiconductor device includes an output driving circuit configured to output an output current to an output terminal; a detection resistor connected between the output terminal and the output driving circuit; an amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor; a current generation circuit configured to output a reference current; a reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current; an A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference; and a control circuit configured to control the output current output from the output driving circuit according to the digital detection signal. The detection resistor has a same temperature characteristics as the reference resistor.

An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.