A programmable a fully-differential programmable gain amplifier for reducing distortion, switching transients and interference, and improving bandwidth. In one embodiment, the amplifier includes a programmable gain module, an amplifier coupled to the current mode outputs and a data latch circuit of the programmable gain module, the amplifier configured to apply common mode voltage to the data latch circuit, and a current-to-voltage converter. In one embodiment, the fully-differential programmable gain amplifier controls distortion and switching interference during amplification by sensing common mode signals to produce an error signal, and applying the resulting error signal to the programmable gain module for multiplying digital to analog conversion. Components of the fully-differential programmable gain amplifier provide compensation of distortion caused by nonlinearity of device switches and switch resistance, and can include a floating supply, galvanic isolation of control signals and a common mode voltage controller.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

A power amplifier with supply switching is provided. The power amplifier detects a magnitude of an outgoing broadband communication signal and determines whether the magnitude exceeds a predetermined voltage threshold. The power amplifier applies a first gain to the outgoing broadband communication signal using a first voltage supply rail when it is determined that the magnitude exceeds the predetermined voltage threshold and a second gain using a second voltage supply rail that is smaller than the first voltage supply rail when it is determined that the magnitude does not exceed the predetermined voltage threshold. The power amplifier produces an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain, wherein a current of the outgoing broadband communication signal is switched between the first voltage supply rail and the second voltage supply rail in response to the magnitude being detected.

A programmable a fully-differential programmable gain amplifier for reducing distortion, switching transients and interference, and improving bandwidth. In one embodiment, the amplifier includes a programmable gain module, an amplifier coupled to the current mode outputs and a data latch circuit of the programmable gain module, the amplifier configured to apply common mode voltage to the data latch circuit, and a current-to-voltage converter. In one embodiment, the fully-differential programmable gain amplifier controls distortion and switching interference during amplification by sensing common mode signals to produce an error signal, and applying the resulting error signal to the programmable gain module for multiplying digital to analog conversion. Components of the fully-differential programmable gain amplifier provide compensation of distortion caused by nonlinearity of device switches and switch resistance, and can include a floating supply, galvanic isolation of control signals and a common mode voltage controller.

A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.

Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.

A differential amplifier circuit includes a first and second amplifiers that output a differential signal in a radio-frequency band, a first inductor having a first end connected to an output end of the first amplifier, a second inductor having a first end connected to an output end of the second amplifier, a choke inductor connected to second ends of the first and second inductors, a first and second capacitors, and a switch that connects the second capacitor in parallel to the first capacitor or terminates a parallel connection of the first and second capacitors. A resonant circuit formed by connecting the first or second inductor in series with the first capacitor has a different resonant frequency from a resonant circuit formed by connecting the first or second inductor in series with the parallel-connected first and second capacitors. These resonant frequencies correspond to second harmonic frequencies of the differential signal.

An operational amplifier includes a first amplifying unit, a second amplifying unit, a current source, a first compensation capacitor, and a second compensation capacitor. The first amplifying unit includes a first input transistor, a second input transistor, a third input transistor, and a fourth input transistor. The second amplifying unit includes a fifth input transistor, a sixth input transistor, a seventh input transistor, and an eighth input transistor. One end of the first compensation capacitor is coupled to a drain of the seventh input transistor, and the other end of the first compensation capacitor is coupled to a gate of the eighth input transistor. One end of the second compensation capacitor is coupled to a drain of the eighth input transistor, and the other end of the second compensation capacitor is coupled to a gate of the seventh input transistor.