A preamplifier including a programmable gain amplifying circuit and a filtering circuit is provided. The programmable gain amplifying circuit has a single output terminal. The filtering circuit includes a first switched-capacitor filter and a second switched-capacitor filter. The first switched-capacitor filter is coupled to the single output terminal. The second switched-capacitor filter is connected in parallel with the first switched-capacitor filter. The first switched-capacitor filter and the second switched-capacitor filter are respectively switched between a first mode and a second mode. When the first switched-capacitor filter is switched to the first mode, the second switched-capacitor filter is switched to the second mode.

In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.

A polarity-switching amplifier circuit includes: a first amplifying transistor and a second amplifying transistor, a transformer which includes a primary winding and a secondary winding, and a polarity-switching controller. An unbalanced input signal is input to the first amplifying transistor and the second amplifying transistor. The transformer receives an output signal of the first amplifying transistor and an output signal of the second amplifying transistor as a balanced signal input to the primary winding, and outputs a signal from the secondary winding. The polarity-switching controller turns on one of the first amplifying transistor and the second amplifying transistor and turns off the other thereof.

An apparatus configured to apply equalization to an input data signal and detect data based on the equalized data signal. The apparatus includes a passive equalizer comprising a first signal path configured to generate a first signal based on an input signal, and a second signal path configured to generate a second signal by filtering the input signal. The apparatus further includes a sense amplifier having an input circuit configured to generate a third signal related to a combination of the first and second signals, and a data detection circuit configured to generate data based on the third signal. The data detection circuit may be configured as a strong-arm latch. The third signal may be a differential current signal including positive and negative current components. The strong-arm latch generating data based on whether the positive current component is greater than the negative current component.

A parallel resonant circuit with excellent distortion and saturation characteristics is provided at low power consumption. A first power-supply voltage is applied to the parallel resonant circuit. In the parallel resonant circuit, a variable resistor includes one or more parallel-connected branches. Each of the branches includes a series circuit of a resistor and a MOS switch. A second power supply supplies power of control signals applied to respective gates of the MOS switches, and supplies back gate voltages to the MOS switches. A power-supply voltage of the second power supply is higher than the first power-supply voltage.

A transformer (2A) outputs differential signals of a positive phase signal (Vout2Ap) having phase 1+90 and a negative phase signal (Vout2An) having phase 190. A transformer (2B) outputs differential signals of a positive phase signal (Vout2Bp) having phase 2+90 and a negative phase signal (Vout2Bn) having phase 290. An adding circuit (3) composes a pair of differential output signals, as signals corrected in phase error (12) generated in the transformers (2A, 2B), in a manner of summing up vectors of two pairs of the differential signals outputted from the transformers (2A, 2B) for the positive phase signal and the negative phase signal, respectively.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.