There is disclosed in one example an integrated circuit, including: a network protocol circuit to provide communication via a network protocol; a network communication terminal having a configurable impedance; and a control circuit including a control input port, and circuitry to adjust the impedance of the network communication terminal responsive to an input signal.

A variable current trans-impedance amplifier (TIA) for an ultrasound device is described. The TIA may be coupled to an ultrasonic transducer to amplify an output signal of the ultrasonic transducer representing an ultrasound signal received by the ultrasonic transducer. During acquisition of the ultrasound signal by the ultrasonic transducer, one or more current sources in the TIA may be varied.

In a sensor reader, an IC chip has a function for amplifying and outputting a sensor signal from each sensor element included in a sensor array, and includes a plurality of channel amplifiers connected each of the sensor elements. When an output switch is closed and the IC chip is in the outputting state, channel switches operate sequentially, and sensor amplification signals are output sequentially from the channel amplifiers. When the output switch is open and the IC chip is in the non-outputting state, a bias current of an operational amplifier of the channel amplifier is decreased, the IC chip is set to a low power consumption state, and gain of the operational amplifier is decreased.

The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.

In a sensor reader, an IC chip has a function for amplifying and outputting a sensor signal from each sensor element included in a sensor array, and includes a plurality of channel amplifiers connected each of the sensor elements. When an output switch is closed and the IC chip is in the outputting state, channel switches operate sequentially, and sensor amplification signals are output sequentially from the channel amplifiers. When the output switch is open and the IC chip is in the non-outputting state, a bias current of an operational amplifier of the channel amplifier is decreased, the IC chip is set to a low power consumption state, and gain of the operational amplifier is decreased.

The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.

An interface for inter-chip communication, comprises a transmitter part (TX) for transmitting a differential signal and a receiver part (RX) for receiving the differential signal, the transmitter part (TX) being provided in a first integrated circuit chip (CHIP A) and the receiver part (RX) being provided in a second integrated circuit chip (CHIP B). The transmitter part (TX) comprises a first transistor (Tx1) and a second transistor (Tx2) arranged in a common source configuration, and the receiver part (RX) comprises a third transistor (TR1) and a fourth transistor (TR2) arranged in a common gate configuration. Current flowing in the receiver part (RX) also flows through the transmitter part (TX).

A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

An interface for inter-chip communication, comprises a transmitter part (TX) for transmitting a differential signal and a receiver part (RX) for receiving the differential signal, the transmitter part (TX) being provided in a first integrated circuit chip (CHIP A) and the receiver part (RX) being provided in a second integrated circuit chip (CHIP B). The transmitter part (TX) comprises a first transistor (Tx1) and a second transistor (Tx2) arranged in a common source configuration, and the receiver part (RX) comprises a third transistor (TR1) and a fourth transistor (TR2) arranged in a common gate configuration. Current flowing in the receiver part (RX) also flows through the transmitter part (TX).