Patent classifications
H03F2203/45702
Differential amplifier circuit having variable gain
A differential amplifier circuit includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generate a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series between the drain and the source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between the gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.
Data storage device employing amplifier feedback for impedance matching
A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a read element configured to generate a read signal when reading data from the magnetic media. A common-source common-gate (CS-CG) differential amplifier is coupled to the read element through a transmission line having a transmission line impedance Z.sub.0. A feedback circuit is coupled between an output of the CS-CG differential amplifier and an input of the CS-CG differential amplifier, wherein the feedback circuit is configured so that an input impedance of the CS-CG differential amplifier substantially matches the transmission line impedance Z.sub.0.
Amplifier circuit with overshoot suppression
An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.
CURRENT MODE LOGIC DRIVER AND TRANSMISSION DRIVER INCLUDING THE SAME
A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.
Photo receiver circuits
Photo receiver circuits comprising photo diode, a first amplifier, a second amplifier, and a feedback resistor are disclosed. The photo diode receives a light signal producing a photo current and the circuit produces an output voltage proportional to the photo current. In one example, the second amplifier coupled across the photo diode provides a voltage level shift between the input terminal and the output terminal, bootstrapping the parasitic capacitance out.
Amplifier circuit
An amplifier circuit is provided, which includes an input stage circuit, at least one impedance component and a current supply circuit, where the input stage circuit is coupled between at least one input terminal of the amplifier circuit and at least one output terminal of the amplifier circuit, the impedance component is coupled between a first reference voltage and the output terminal, and the current supply circuit is coupled between a second reference voltage and the output terminal. The input stage circuit is arranged to generate a signal current in response to an input signal on the input terminal, and the current supply circuit is arranged to provide at least one adjustment current. In addition, a common mode voltage level of an output signal on the output terminal is controlled by the adjustment current, to allow the amplifier circuit to perform low voltage operations.
Amplifier with common mode detection
An analog discrete current mode negative feedback amplifier circuit for use with a micro-fused strain gauge is disclosed. The amplifier circuit includes a Wheatstone bridge coupled to a first power supply and a second power supply. The first power supply and the second power supply can be configured such that the periodically alternate between two voltage levels. The Wheatstone bridge can be coupled to a negative feedback amplifier circuit with common mode detection. The amplifier circuit can comprise a differential amplifier with a negative feedback configuration coupled to a common mode amplifier. In addition, the output of each of the amplifiers can be coupled to a common-mode amplifier. In a pressure sensing application, the output of the common mode amplifier serves to output the temperature while the differential amplifiers serve to output the pressure.
DIFFERENTIAL AMPLIFIER CIRCUIT HAVING VARIABLE GAIN
A differential amplifier circuit disclosed includes a first transistor, a second transistor, a field effect transistor (FET) connected between the first transistor and the second transistor, a first current source connected to the first transistor, a second current source connected to the second transistor, and a control circuit. The first transistor and the second transistor generates a differential output signal in accordance with an input signal and a reference signal. The control circuit includes a first resistor and a second resistor connected in series to each other between drain and source of the FET, a center node between the first resistor and the second resistor, a third resistor connected between gate of the FET and the center node, and a variable current source. The variable current source supplies a control current to the third resistor in accordance with a gain control signal. The control circuit controls on-resistance of the FET.
Transmission device and transmission/reception system
A transmission/reception system 1 includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P.sub.111 and P.sub.112 that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P.sub.111 and P.sub.112 is constant over a state where no electric power is supplied and an idle state.
Apparatus and a method for amplifying an input signal
An apparatus for amplifying an input signal is provided. The apparatus includes an output stage to generate an output signal. The apparatus further includes a compensation signal generator configured to generate a compensation signal based on at least one of a voltage value of the input signal or a voltage value of the output signal. The apparatus further includes a combiner configured to generate a control signal for the output stage based on a target signal, the compensation signal and a signal related to a current value of the output stage. The target signal corresponds to a desired output signal. The output stage is configured to generate the output signal using the control signal.